Not able to set EMC clock to maximum frequency

Autonomous Machines Jetson & Embedded Systems Jetson TX1
1

Running the jetsion_clocks.sh script provided in the L4T distribution is correctly setting the CPUs and GPUs to their Maximum frequency, but the EMC clock is still set at 204 MHz.

root@tegra-ubuntu:/home/ubuntu# ./jetson_clocks.sh 
root@tegra-ubuntu:/home/ubuntu# ./jetson_clocks.sh --show
SOC family:tegra210  Machine:jetson_tx1
Online CPUs: 0-3
CPU Cluster Switching: Disabled
cpu0: Gonvernor=interactive MinFreq=1734000 MaxFreq=1734000 CurrentFreq=1734000
cpu1: Gonvernor=interactive MinFreq=1734000 MaxFreq=1734000 CurrentFreq=1734000
cpu2: Gonvernor=interactive MinFreq=1734000 MaxFreq=1734000 CurrentFreq=1734000
cpu3: Gonvernor=interactive MinFreq=1734000 MaxFreq=1734000 CurrentFreq=1734000
GPU MinFreq=998400000 MaxFreq=998400000 CurrentFreq=998400000
EMC MinFreq=12750000 MaxFreq=1600000000<b> <u>CurrentFreq=204000000 FreqOverride=1</u></b>
Fan: speed=255

I have also tried directly writing to the /sys/debug entries as shown in the L4T development guide with the same result, the EMC frequency stays at 204 MHz.

echo 1600000000 > /sys/kernel/debug/clk/override.emc/clk_update_rate
echo 1 > /sys/kernel/debug/clk/override.emc/clk_state

Is there some other power management or frequency scaling setting that I need to set as well to force the memory to always run at the maximum frequency.

Thanks!

2

Hi wkrit,

I can modify the emc frequency by your method. Could you give out the dmesg when you override the emc clk?

3

Hi Wayne,
Here is the dmesg output after I try to run the jetson_clocks.sh script. THe EMC clock is still set to 204 MHz.

[   62.756213] gk20a 57000000.gpu: railgate is disabled.
[  415.396211] Setting pll_a = 45158400 Hz clk_out = 11289600 Hz
[  415.442578] Setting pll_a = 45158400 Hz clk_out = 11289600 Hz
[  415.474898] Setting pll_a = 45158400 Hz clk_out = 11289600 Hz
[  415.511239] Setting pll_a = 45158400 Hz clk_out = 11289600 Hz
[  415.520491] Setting pll_a = 45158400 Hz clk_out = 11289600 Hz
[  415.530597] Setting pll_a = 45158400 Hz clk_out = 11289600 Hz
[  415.558713] Setting pll_a = 45158400 Hz clk_out = 11289600 Hz
[  415.567726] Setting pll_a = 45158400 Hz clk_out = 11289600 Hz
[  415.589427] Setting pll_a = 45158400 Hz clk_out = 11289600 Hz
[  540.686312] Setting pll_a = 45158400 Hz clk_out = 11289600 Hz

Looking into the kernel source we noticed that it would not set the EMC clock to a given rate if the EMC training was not successful. I attached a serial port to the board and can see the following successful EMC training.

[0001.391] Total time taken by TegraBoot 1242014 us

[0001.396] Starting CPU & Halting co-processor 

64NOTICE:  BL31: v1.2(release):cc5fd7c
NOTICE:  BL31: Built : 00:37:02, Jul 20 2017
NOTICE:  Trusty image missing.
ERROR:   Error initializing runtime service trusty_fast
[0001.536] RamCode = 0
[0001.558] LPDDR4 Training: Read DT: Number of tables = 10
[0001.563] EMC Training (SRC-freq: 204000; DST-freq: 40800)
[0001.568] EMC Training Skipped
[0001.571] EMC Training (SRC-freq: 204000; DST-freq: 68000)
[0001.576] EMC Training Skipped
[0001.579] EMC Training (SRC-freq: 204000; DST-freq: 102000)
[0001.584] EMC Training Skipped
[0001.587] EMC Training (SRC-freq: 204000; DST-freq: 204000)
[0001.592] EMC Training Skipped
[0001.595] EMC Training (SRC-freq: 204000; DST-freq: 408000)
[0001.601] EMC Training Successful
[0001.604] EMC Training (SRC-freq: 204000; DST-freq: 665600)
[0001.610] EMC Training Successful
[0001.613] EMC Training (SRC-freq: 204000; DST-freq: 800000)
[0001.624] EMC Training Successful
[0001.627] EMC Training (SRC-freq: 204000; DST-freq: 1065600)
[0001.650] EMC Training Successful
[0001.653] EMC Training (SRC-freq: 204000; DST-freq: 1331200)
[0001.675] EMC Training Successful
[0001.678] EMC Training (SRC-freq: 204000; DST-freq: 1600000)
[0001.697] EMC Training Successful
[0001.701] Switching to 800000 KHz Success
[0001.710] RamCode = 0
[0001.714] DT Write: emc-table@40800 succeeded
[0001.721] DT Write: emc-table@68000 succeeded
[0001.727] DT Write: emc-table@102000 succeeded
[0001.733] DT Write: emc-table@204000 succeeded
[0001.739] DT Write: emc-table@408000 succeeded
[0001.745] DT Write: emc-table@665600 succeeded
[0001.751] DT Write: emc-table@800000 succeeded
[0001.757] DT Write: emc-table@1065600 succeeded
[0001.763] DT Write: emc-table@1331200 succeeded
[0001.769] DT Write: emc-table@1600000 succeeded
[0001.774] LPDDR4 Training: Write DT: Number of tables = 10

I should have stated this earlier, but I have a Jetson TX1 developement board , with L4T v28.1. The additional software we have installed above the L4T distribution does not modify the kernel or device tree at this time.

4

Hello again,
We ended up just re-flashing the development board with L4T 28.1 plus our software and the EMC clock problem went away. I can now again use the jetson_clocks.sh script as-is to set the CPU, GPU and EMC clocks all to their maximum values.