Change TX1 LPDDR4 memory frequency

The standard TX1 LPDDR4 operating frequency seems to be 1600Mhz. I would like to reduce that frequency to 800Mhz. How do you do that?

Hello - can I get some help from the Dev Team?

Hello, fps:
Generally, DDR clock is controlled by DVFS in kernel, and it may change according to current DDR bandwidth usage.

You can limit the max freq of DDR by the following command:
sudo su
echo 800 >/sys/kernel/debug/clock/emc/max

Let me know if there’s any other issue.

br
ChenJian

Hello ChenJian:

We used this command and it did not change the standard LPDDR4 frequency behavior of the Jetson TX1 at all.

The system starts at 400MHz and then switches to a clock rate of 1600MHz with any user input.

Please provide us a means to limit the upper operating frequency to 800MHz.

fps

Hi,

The following command is working for me, can you try it again?(note the value we echo should be in Hz, neither KHz, nor MHz)

echo 800000000 > /sys/kernel/debug/clock/emc/max

Hello - Is there a way to FIX the LPDDR4 frequency and stop it from shutting the LPDDR4 clock off?

Hello,
you can fix the DDR clock by following command (with ‘root’)

echo 800000000 >/sys/kernel/debug/clock/emc/max
cat /sys/kernel/debug/clock/emc/max >/sys/kernel/debug/clock/override.emc/rate
echo 1 >/sys/kernel/debug/clock/override.emc/state

br
Chenjian

Hello Chenjian:

This command string does not fix the LPDDR4 clock. It is still turning on and off.

Please help.

Hello, fps:
Can you share your detailed test steps and ‘tegrastats’ result log?

Paste my log for your reference.

Without running the command, before and after ‘stress -c 4 -i 4’ tegrastats result :

RAM 1270/3994MB (lfb 547x4MB) cpu [3%,5%,0%,0%]@102 EMC 11%@665 AVP 66%@12 GR3D 0%@76 EDP limit 1734
RAM 1270/3994MB (lfb 547x4MB) cpu [2%,3%,0%,0%]@102 EMC 11%@665 AVP 66%@12 GR3D 0%@76 EDP limit 1734
RAM 1270/3994MB (lfb 547x4MB) cpu [3%,5%,0%,0%]@102 EMC 11%@665 AVP 66%@12 GR3D 0%@76 EDP limit 1734
RAM 1270/3994MB (lfb 547x4MB) cpu [44%,45%,42%,43%]@1734 EMC 5%@1600 AVP 38%@12 GR3D 0%@76 EDP limit 1734
RAM 1270/3994MB (lfb 547x4MB) cpu [100%,100%,100%,100%]@1734 EMC 6%@1600 AVP 11%@12 GR3D 0%@76 EDP limit 1734
RAM 1270/3994MB (lfb 547x4MB) cpu [100%,100%,100%,100%]@1734 EMC 7%@1600 AVP 4%@12 GR3D 0%@76 EDP limit 1734
RAM 1270/3994MB (lfb 547x4MB) cpu [100%,100%,100%,100%]@1734 EMC 7%@1600 AVP 4%@12 GR3D 0%@76 EDP limit 1734
RAM 1270/3994MB (lfb 547x4MB) cpu [100%,100%,100%,100%]@1734 EMC 7%@1600 AVP 4%@12 GR3D 0%@76 EDP limit 1734
RAM 1270/3994MB (lfb 547x4MB) cpu [100%,100%,100%,100%]@1734 EMC 7%@1600 AVP 4%@12 GR3D 0%@76 EDP limit 1734
RAM 1270/3994MB (lfb 547x4MB) cpu [100%,100%,100%,100%]@1734 EMC 7%@1600 AVP 4%@12 GR3D 0%@76 EDP limit 1734
RAM 1270/3994MB (lfb 547x4MB) cpu [53%,55%,52%,52%]@102 EMC 15%@665 AVP 27%@12 GR3D 0%@76 EDP limit 1734
RAM 1270/3994MB (lfb 547x4MB) cpu [2%,6%,0%,0%]@102 EMC 11%@665 AVP 55%@12 GR3D 0%@76 EDP limit 1734
RAM 1270/3994MB (lfb 547x4MB) cpu [0%,2%,0%,0%]@102 EMC 11%@665 AVP 62%@12 GR3D 0%@76 EDP limit 1734
RAM 1270/3994MB (lfb 547x4MB) cpu [2%,5%,0%,0%]@102 EMC 11%@665 AVP 70%@12 GR3D 0%@76 EDP limit 1734

EMC clock changes when system loading changes.

After command running, the tegrastats result:

RAM 1270/3994MB (lfb 547x4MB) cpu [1%,4%,0%,0%]@102 EMC 9%@800 AVP 63%@12 GR3D 0%@76 EDP limit 1734
RAM 1270/3994MB (lfb 547x4MB) cpu [1%,4%,0%,0%]@102 EMC 9%@800 AVP 63%@12 GR3D 0%@76 EDP limit 1734
RAM 1270/3994MB (lfb 547x4MB) cpu [2%,3%,0%,0%]@102 EMC 9%@800 AVP 63%@12 GR3D 0%@76 EDP limit 1734
RAM 1270/3994MB (lfb 547x4MB) cpu [1%,4%,0%,0%]@102 EMC 9%@800 AVP 63%@12 GR3D 0%@76 EDP limit 1734
RAM 1271/3994MB (lfb 547x4MB) cpu [70%,70%,68%,67%]@1734 EMC 10%@800 AVP 27%@12 GR3D 0%@76 EDP limit 1734
RAM 1271/3994MB (lfb 547x4MB) cpu [100%,100%,100%,100%]@1734 EMC 11%@800 AVP 7%@12 GR3D 0%@76 EDP limit 1734
RAM 1271/3994MB (lfb 547x4MB) cpu [100%,100%,100%,100%]@1734 EMC 12%@800 AVP 7%@12 GR3D 0%@76 EDP limit 1734
RAM 1271/3994MB (lfb 547x4MB) cpu [49%,51%,48%,48%]@102 EMC 11%@800 AVP 35%@12 GR3D 0%@76 EDP limit 1734
RAM 1270/3994MB (lfb 547x4MB) cpu [1%,6%,0%,0%]@102 EMC 9%@800 AVP 57%@12 GR3D 0%@76 EDP limit 1734
RAM 1270/3994MB (lfb 547x4MB) cpu [1%,4%,0%,0%]@102 EMC 9%@800 AVP 57%@12 GR3D 0%@76 EDP limit 1734

EMC clock is fixed @ 800MHz regardless of system loading.

br
Chenjian

Hello Chenjian:

You do not understand our request.

We want to keep the LPDDR4 clock on ALL THE TIME.

The LPDDR4 clock runs at 800MHz, but it turns on (800 MHz) and off (no clock transitions).

How do we keep the LPDDR4 clock on ALL THE TIME?

Torry

Hello,
I’m a little confuse about your words. What do you mean ‘off (no clock transitions).’?

Generally, DDR clock will not turn off. In what case you see DDR clock OFF?

br
Chenjian

Hello,

The nVidia Jetson TX1 board turns off the LPDDR4 bus clock. If you put a scope on the CK0 differential signal you see no signal swing at all. This happens about 30% of the time under all circumstances when the Jetson board is booted and running Ubuntu. I have a scope shot on Dropbox that shows this:

This appears to be the normal operating mode of the nVidia Jetson TX1 platform. The LPDDR4 clock will also change frequency from 400MHz to 1600MHz, when the clock is operating, but we have changed that with the software instructions detailed above so that when the LPDDR4 clock is operating it runs at only 800MHz.

Our question to NVidia is - How can we keep the LPDDR4 clock running at a fixed frequency of 800MHz at all times?

Torry

Hi fps,

Gating clock when no workload will reduce power consumption. Can you tell why you want to keep clock running at all times?

Hello Trumany:

Yes, we are aware of that.

This is an open forum and we do not want to discuss the background for our request in such a place. If NVidia requires a detailed explanation of our need please provide me your work email.

Our request made over 1 month ago (7/8/16) to nVidia for information on how to keep the LPDDR4 clock at a fixed frequency at all times and not turn it off (gate it) is still open.

Can you help us?

Torry

Hi fps,

We’re investigating this issue further, status or suggestion will be updated once clarified and concluded.

Thanks