Jetson AGX Orin HW FAQ

Q1: Flashing over USBSS.

Flashing over USBSS is now supported referring to Flashing Support — Jetson Linux Developer Guide documentation

Q2: Is the DC Jack on Xavier devkit compatible to that of Orin?

Yes, they are compatible, and some customer validated that.

Q3: What is the Orin power consumption of SC7?

The CVM power at SC7 is ~300mW. The CVM+CVB total power is close to 1.1W.

Q4: RTC0 or RTC1 for default RTC clock during power off?

The Original default RTC source is set as RTC1 (Orin_RTC), which can not keep time if power off. So a patch to set default RTC to RTC0 (PSEQ_RTC) is needed.

Q5: Does MGBE lines support P/N reversal?

Yes, the 10G ethernet PHY support P/N correction automatically. To make the trace smooth, we swap P and N.

Q6: What is the usage of pin MOD_TEMP_SHDN_EN_N (J62) in P3737_A04?

MOD_TEMP_SHDN_EN_N is not used on commercial module. It is for Auto/industrial module to gate buffers of temp_therm and soc_pwr_req. Suggest to short to GND to keep the messaging consistent across all modules: floating = TEMP_THERM and SOC_PWR_REQ gated, GND= un-gated.

Q7: Is there a signal output can be used to indicate a SW RESET thing?

There is no explicit pin on Orin that indicates an internal SW reset has occurred. Internal SW reset does not propagate to the IO pin. One way to set an indicator is to use the internal watchdog timer and use WDT_RESET_OUTA (GP63) or WDT_RESET_OUTB (GP21) as the indicator. Both signals are available on the CVM connector.

Q8: Why there is no PCIe inter-skew spec in Design Guide?

PCIe pair to pair requirement was so loose (5~20ns), it would be nearly impossible to violate and still meet the max lengths (1.185~2.987ns)

Q9: Can use2.0 port from a hub combine with USBSS port directly?

One USB2 roothub cannot be paired with multiple USB3 roothubs. Valid design is one USB2 roothub + one USB3 roothub like:

*) USB2 + USB3 in pair connecting to a USB HUB

*) USB2 + USB3 in pair connecting to a PD controller and then to a type-C port

*) USB2 + USB3 in pair connecting to a type-A port

Q10: Can CLK_32K_OUT buffer be omitted on the carrier board?

The buffer on carrier is 74LVC1G07GW which supports open-drain function and so can be used for 3.3V. While the buffer on module is 74LVC2G125 without OD support.

Q11: How many standing force of SoM is OK when attached/fixed a heat sink on SoM?

We didn’t do loading test or pressure test on Stardust in qualification test. We did mechanical shock, drop, assembly test, as they are more representative to the stress in the field.

Q12: What is the operating voltage of RTC?

The level could be 1.65V ~ 5.5V per PMIC datasheet.

Q13: Does devkit support hotplug module?

Please do NOT hotplug module as it could damage board. And also please install the two fix screws during any use case to guarantee module is attached to carrier good enough.

Q14: What’s the weight of Orin nano and Orin devkit?

Weight of Orin nano devkit is 0.174kg. Orin devkit is 872.5g.

Q15: Does Orin support XAUI/RXAUI?

No, it is not supported on Orin.

Q16: Is the soldermask used on the Jetson AGX Orin module outgas compliant per ASTM E595?

The solder mask type used is Taiyo PSR-4000MEH/CA-40 G23K. It has not been tested to the ASTM E595 standard.

Q17: How to config pins with 3.3v tolerance enabled/disabled?

An external pull-up is necessary for the GPIO pin if its “3.3v tolerance” is enable. If do not need to enable 3.3v tolerance, below setting in dts is necessary then.
“nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;”

Q18: What are the difference between “Board-level” and “System-level” in module data sheet?

Board-level is PCBA qualification test, checking the quality of PCBA. It’s based on JEDEC standard.

System-level is to test the whole system. It’s more usage condition-oriented, simulating real usage scenario. It’s based on IEC or ISO standards. system-level is the whole system including cooling fans, power adapter, chassis, housing, etc.

Q19: What is the RTC accuracy on Orin?

Orin: +/-11s/day.
Orin NX/Nano: -11s ~+20s/day.

Q20: What can do if the wifi module in SCL is EOL?

  1. The wifi module we include in the developer kit is what we validate out of box and is included in Support Component List.
  2. For other Wifi solutions, please work with NV ecosystem partners (Infineon and Silex) who provide validated wifi solutions on Jetson: Jetson Ecosystem | NVIDIA Developer
  3. For solutions other than in Support Component List and ecosystem partners, customers should work with the vendor directly.

Q21: How to do stress test for Orin?

Refer to the guideline in Jetson/L4T/TRT Customized Example -

  1. Please find matrixMulCUBLAS sample under /usr/local/cuda-11.4/samples/0_Simple/.

  2. Apply 0001-half-matrixMulCUBLAS.patch to change data type into half.

  3. Boost device

    $ sudo nvpmodel -m 0
    $ sudo jetson_clocks

  4. Run matrixMulCUBLAS and stress in different console

    $ ./matrixMulCUBLAS
    $ stress --cpu $(nproc)

Q22: Should deskew be enabled for CSI?

Deskew is to perform high-speed skew-calibration between clock and data lanes. According to MIPI_D-PHY_specification_v1-2, transmitter shall send deskew pattern when operating above 1.5 Gbps or changing to any rate above 1.5 Gbps. An initial deskew sequence shall be transmitted before High-Speed Data Transmission in normal mode. For C-PHY, calibration shall be suppoted by Transmitters and Receivers that operate above 3.0 Gsps.

Q23: Does USB2 lines support polarity inversion?

USB2 polarity is defined and cannot be changed. The statement in the design guide is only for the SS, SS_TX_* and SS_RX_*. Refer to the spec, the polarity would be checked with TSEQ and thus it is OK to do the P/N swap on SS differential pairs. For USB2, there’s no such mechanism to check the polarity.

Q24: Why does Orin AGX SRNS clocking is recommended?

SRNS clocking is recommended in DG as it can provide clock to EP even if RP is dead. There might be FCC issue which needs customer to make shielding design.

Q25: What’s the impact of SSC to PCIe Refclk Frequency range?

The spec of REFCLK is 99.97 ~ 100.03Mhz, while customer found it is 99.78/99.77Mhz on devkit and custom board. Internal discussion about this is ongoing, as per the spec of REFCLK with SSC, it will bring in -300~+2800 ppm deviation and so the freq spec will be 99.72 ~ 100.03Mhz.

Q26: What’s the SC7 power consumption of Orin series module?

Orin 32GB:
The CVM power at SC7 is ~300mW. The CVM+CVB total power is close to 1.0W. The carrier board consumes close to 700mW power.

Orin 64GB:
The CVM power at SC7 is ~350mW. The CVM+CVB total power is close to 1.1W. The carrier board consumes close to 750mW power.

Jetson AGX Orin Industrial:
The CVM power at SC7 is ~400mW. The CVM+CVB total power is close to 1.2W. The carrier board consumes close to 800mW power.

Q27: What’s the meaning of the ‘x’ in the POR column in pinmux sheet?

The UPHY IO POR state is in idle state and output “zero-differential” signal. This state is not “0”, “1”, or “z” and so “x” is used for “zero-differential” state.

Q28: What’s the recommended screw size for Orin module?

M2.5 (2.5mm) and M3 (3mm) screws are recommended for Orin series modules as the mounting holes are ф3.5mm.

Q29: Why is the Orin UPHY S-parameter unidirectional?

UPHY’s on-die termination model is unidirectional and the valid path is only from on-die to BGA for TX, and from BGA to on-die for RX.

Q30: What is the function of HS_DIN_DLY_SEL in USB2 Eye diagram test?

HS_DIN_DLY_SEL is pre-emphasis bit to control half bit or 1 bit duration boot, default should be 0x0 (which to boost duration of rising edge). HS_DIN_DLY_SEL=1 setting should be better for long cable. (enhance 1 bit instead of 0.5bit)

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