Hello Nvidia,
We are working on Jetson AGX orin industrial version module mounted on custom carrier board. We were trying to bringup RGMII interface with PHY chip DP83867 but unable to make it work below are the background of our setup:
Jetpack version- 36.4.3
Pinmux - gpio.txt (2.9 KB)pinmux.txt (65.7 KB)
Device Tree node of RGMII -
ethernet@2310000 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ext_phy>;
nvidia,mac-addr-idx = <0>;
nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(G, 5) 0>;
mdio {
compatible = "nvidia,eqos-mdio";
#address-cells = <1>;
#size-cells = <0>;
ext_phy: phy@0 {
reg = <1>;
compatible = "ti,dp83867";
nvidia,phy-rst-pdelay-msec = <224>; /* msec */
nvidia,phy-rst-duration-usec = <10000>; /* usec */
tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,max-output-impedance;
ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_RCLK>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
};
};
};
DP83867 enable in kernel config-
CONFIG_DP83867_PHY=y
Below are the error messages of RGMII-
[ 11.723712] nvethernet 2310000.ethernet: Adding to iommu group 54
[ 11.852473] nvethernet 2310000.ethernet: failed to read skip mac reset flag, default 0
[ 11.852483] nvethernet 2310000.ethernet: failed to read MDIO address
[ 11.852488] nvethernet 2310000.ethernet: setting to default DMA bit mask
[ 12.141366] nvethernet 2310000.ethernet: Ethernet MAC address:48:b0:2d:94:ac:d
[ 12.205933] nvethernet 2310000.ethernet: Macsec not enabled
[ 12.214332] nvethernet 2310000.ethernet: eth1 (HW ver: 53) created with 8 DMA channels
[ 12.563479] mdio_bus 2310000.ethernet: MDIO device at address 0 is missing.
[ 12.563531] nvethernet 2310000.ethernet: failed to connect PHY
[ 20.163987] mdio_bus 2310000.ethernet: MDIO device at address 0 is missing.
[ 20.172251] nvethernet 2310000.ethernet: failed to connect PHY
[ 20.179193] net eth0: ether_open: Cannot attach to PHY (error: -19)
Along with above messages we are seeing a fixed behavior when we probed the Reset, MDC and MDIO lines which is-
When Module power ON we can see activity on MDC and MDIO lines also reset is high at this time.
Reset will high during whole boot process but as soon as board boots up the reset goes low and it will be always low never goes to high.
During this process there is no activity on MDC and MDIO lines.
Note: we do full flash of module every time during RGMII changes to reduce any flashing related issues.
kayccc
February 25, 2026, 6:53am
4
Sorry for the late response.
yes its still an issue. I am eagerly waiting for nvidia response. My development work is pending.
HI,
It seems you are having similar issues to what I am having with the TI DP83869 PHY on the RGMII interface. Please see my thread here: Jetson Orin AGX EQOS MAC issues with customer carrier board and TI PHY - Jetson Systems / Jetson AGX Orin - NVIDIA Developer Forums
In the middle of the thread (Feb 24th) there is my tegra234-tpcca+p3701-0008_dts.txt file which is the dts file I am using with a full entry for the ethernet@2310000.
Most of the extra comes from the /Linux_for_Tegra/source/hardware/nvidia/t23x/nv-public/nv-soc/tegra234-base-overlay.dtsi file.
Hope this helps.
Jim
Hello Nvidia,
Are you sure the hardware MDIO address is on address 0? This should be decided by hardware strap pin.
Hi WayneWWW,
Yes the Address is 10 because my Hardware team made it to 10 when phy address 0 isnt working in earlier configuration.
Here is the latest dts for phy address 10-
phy-mode = "rgmii-id";
phy-handle = <&ext_phy>;
nvidia,mac-addr-idx = <0>;
nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(G, 5) 0>;
mdio {
compatible = "nvidia,eqos-mdio";
#address-cells = <1>;
#size-cells = <0>;
ext_phy: phy@10 {
reg = <10>;
compatible = "ti,dp83867";
nvidia,phy-rst-pdelay-msec = <224>; /* msec */
nvidia,phy-rst-duration-usec = <10000>; /* usec */
interrupt-parent = <&gpio>;
interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
ti,rx-internal-delay = <0x7>;
ti,tx-internal-delay = <0x7>;
};
};
};
but still error messages are same.
please configure nvidia,mdio_addr in the device tree to 10 to meet your board design.
should I add this nvidia,mdio_addr property in current node after this line>nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(G, 5) 0>; ?
As per your suggestions, we have made the changes below.
ethernet@2310000 {
phy-mode = "rgmii-id";
phy-handle = <&ext_phy>;
nvidia,mac-addr-idx = <0>;
nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(G, 5) GPIO_ACTIVE_HIGH>;
nvidia,mdio_addr = <10>;
mdio {
compatible = "nvidia,eqos-mdio";
#address-cells = <1>;
#size-cells = <0>;
ext_phy: phy@10 {
reg = <10>;
compatible = "ti,dp83867";
nvidia,phy-rst-pdelay-msec = <224>; /* msec */
nvidia,phy-rst-duration-usec = <10000>; /* usec */
interrupt-parent = <&gpio>;
interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_RCLK>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
};
};
};
We still encounter the same errors. Kindly help.
kayccc
April 22, 2026, 5:32am
16
Is this still an issue to support? Any result can be shared?
Hi
share the log file please.
Hi,
Please find the log attached herewith. Right now, we see no activity on the logic analyser. Your help would be appreciated. Thanks.
please share me a whole text file without doing any parsing here.
Also, what it looks like reset gpio is not set again?
log.txt (58.3 KB)
[ 10.697423] nvethernet 2310000.ethernet: failed to get phy reset gpio error: -2
I am not sure what to elaborate here.
You set
Hi!
ethernet@2310000 {#address-cells = <1>;#size-cells = <0>;
Orin_log_12_1.docx (39.9 KB)
