Jetson Nano DevKit - can't operate with PCIe switch

Autonomous Machines Jetson & Embedded Systems Jetson Nano
1

I used the M.2 interface in the Jetson Nano DevKit to connect to SSD via PCIe switch. I tried PLX Switch, ASM Media Switch, and PLDA Switch.
With all of them, the switch and the SSD were not recognized by the RC (in lspci).
BUT, when connecting the SSD directly to the Nano, linux disk benchmark test results indicated good performance ~3.2Gb/s

Does someone encounter this kind of problem?

2

A couple of questions…
Is your SSD an M.2 Key-E slot compatible SSD? (Given that it gets enumerated correctly when connected directly, I think it is M.2 Key-E compatible, but asking just to confirm the same)
Is your switch also M.2 Key-E slot compatible? If not, are you connecting any slot converter cable to convert M.2 Key-E to normal slot? If yes, did you happen to verify that cable by connecting to any other system and getting things working fine?

3

The M.2 slot interface of the Nano is exported using adapter (like this one: https://ae01.alicdn.com/kf/HTB1aO8FXjDuK1Rjy1zjq6zraFXaZ/M-2-WiFi-A-E-Key-A-E-To-PCI-e-4x-x4-Riser-Extender-Adapter.jpg)
When the SSD was inserted in the adapter - very good results.
When connecting the PCIe switch - problem.

4

Does your switch need +12V as well? Because M.2 Key-E doesn’t have support for +12V. Please check that.

5

I know the M.2 supports only +3.3V so I used the option on the adapter to drive the +12V externally.
The problem occur also when the +12V is driven.

6

I’m not sure if the adapter cable that is being connected here has any issues with CLKREQ signal.
Can you please apply the below patch and check once?

--- a/drivers/pci/dwc/pcie-tegra.c
+++ b/drivers/pci/dwc/pcie-tegra.c
@@ -4535,6 +4535,11 @@ static int tegra_pcie_dw_runtime_resume(struct device *dev)
        val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT);
        writel(val, pcie->appl_base + APPL_CFG_MISC);

+       val = readl(pcie->appl_base + APPL_PINMUX);
+       val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN;
+       val &= ~APPL_PINMUX_CLKREQ_OVERRIDE;
+       writel(val, pcie->appl_base + APPL_PINMUX);
+
        if (pcie->disable_clock_request) {
                val = readl(pcie->appl_base + APPL_PINMUX);
                val |= APPL_PINMUX_CLKREQ_OUT_OVRD_EN;
7

I can’t find /drivers/pci/dwc/pcie-tegra.c

8

You should be able to find this in $TOP/kernel/nvidia/ path. (All other kernel files are typically found in $TOP/kernel/kernel-4.9/ folder)

9

I couldn’t find it

10

Apologies for pointing to a wrong file.
Please add “nvidia,disable-clock-request” for all the root port nodes under main PCIe node in device-tree?
This would confirm that the issue is caused by missing CLKREQ routing.

11

Can you please point me to the location of the device tree?

12

In addition, is this solution valid for both DevKit versions, A00 and B01?

13

Hi matan.hershkovitz,

Please help to open a new topic for your issue. Thanks