I’m trying to communicate with an IMX264 sensor on a custom board. The problem is that I had to use SPI mode 3 but the CLK signal didn’t stay at high level when not used.
Like we can see on the oscilloscope (nCS in blue and CLK in yellow), the chip select falls and then the clock rises. In SPI mode 3 value are taken on rising edge of the CLK so I want that CLK rises before chip select falls. How can I do this?
It’s a GPIO chip select.
The SPI ports on the 40-pin header are software emulated and there is a bug in that software that causes the problem you are seeing. It is the exact same problem I saw.
Nvidia support pointed me to a kernel patch to try, but I never did. Instead I used a standard inverter on the clock so I could use one of the SPI modes that didn’t show the bug (any mode where CLK is idle low). As long as the inverter is reasonably fast (most are) then everything works very well.