TK1 SPI CS 21.7

Hi,

We had to upgrade from 21.3 to 21.7 due to our new camera. But the chip select seems to misbehave, when analyzing the analog cs signal it slowly drops - see:

https://imgur.com/a/8mR8Gfr

Is there anything we can do with our dts? I’m not highly experienced at this level of spi configuration, our dts looks as follows:

spi@7000d400 {
                compatible = "nvidia,tegra114-spi";
                reg = <0x0 0x7000d400 0x0 0x200>;
                interrupts = <0x0 0x3b 0x4>;
                nvidia,dma-request-selector = <0x7 0xf>;
                nvidia,memory-clients = <0xe>;
                #address-cells = <0x1>;
                #size-cells = <0x0>;
                clocks = <0xc 0x29>;
                status = "okay";
                dmas = <0x7 0xf 0x7 0xf>;
                dma-names = "rx", "tx";
                spi-max-frequency = <0x17d7840>;

                spi0_0@0 {
                        #address-cells = <0x1>;
                        #size-cells = <0x0>;
                        compatible = "spidev";
                        reg = <0x1>;
                        spi-max-frequency = <0x17d7840>;
                        spi-cpha;
                        nvidia,enable-hw-based-cs;
                        nvidia,cs-setup-clk-count = <0x1e>;
                        nvidia,cs-hold-clk-count = <0x1e>;
                        nvidia,rx-clk-tap-delay = <0x1f>;
                        nvidia,tx-clk-tap-delay = <0x0>;
                };

Please have a check below topic.

https://devtalk.nvidia.com/default/topic/987210

Hi ShaneCCC,

Thank you for your answer. I already applied the patch from your post to the code. I’m not sure if that was what you’re referring to. I don’t know what to set nvidia,clk-delay-between-packets to or nvidia,chipselect-gpio for that matter. Can you provide a bit more guidance? I played with the nvidia,clk-delay-between-packets a little, but it didn’t seem to have an effect at all.

Kind regards,
Error323

Did you add something like below below to your DT?

	spi@0 {
		spi-max-frequency = <4000000>;
		controller-data {
			nvidia,clk-delay-between-packets = <10>;
			nvidia,chipselect-gpio = <xx 0>;
		};
	};

Hi Error323,

Have you clarified the cause and resolve the problem?
Any update?

Thanks

Hi kayccc,

I’ll have an update today on the issue! Hooking up the analyzer now. Hopefully your fix resolves it.

Thanks

Hi kayccc,

Unfortunately it doesn’t seem to help. Here is the current spi snippet from the dts file:

spi@7000d400 {
                compatible = "nvidia,tegra114-spi";
                reg = <0x0 0x7000d400 0x0 0x200>;
                interrupts = <0x0 0x3b 0x4>;
                nvidia,dma-request-selector = <0x7 0xf>;
                nvidia,memory-clients = <0xe>;
                #address-cells = <0x1>;
                #size-cells = <0x0>;
                clocks = <0xc 0x29>;
                status = "okay";
                dmas = <0x7 0xf 0x7 0xf>;
                dma-names = "rx", "tx";
                spi-max-frequency = <0x17d7840>;

                spi0_0@0 {
                        #address-cells = <0x1>;
                        #size-cells = <0x0>;
                        compatible = "spidev";
                        reg = <0x1>;
                        spi-max-frequency = <0x17d7840>;
                        spi-cpha;
                        nvidia,enable-hw-based-cs;
                        nvidia,cs-setup-clk-count = <0x1e>;
                        nvidia,cs-hold-clk-count = <0x1e>;
                        nvidia,rx-clk-tap-delay = <0x1f>;
                        nvidia,tx-clk-tap-delay = <0x0>;
                        controller-data {
                                nvidia,clk-delay-between-packets = <10>;
                                nvidia,chipselect-gpio = <0x0>;
                        };
                };
        };

And here’s the spi readout when sending “Hello world!” as root on the tk1: https://i.imgur.com/anM8h3K.png

The chip select seems to drop way to slow and too late. Any idea what’s wrong?

The following dmesg wrt spi also pops up:

root@init:/usr/src/kernel# dmesg | grep -i spi
[    0.513953] avdd-spi: 3300 mV at 150 mA 
[    4.243813] spi spi0.1: CS GPIO is not found on node controller-data: -2
[    7.252334] avdd-spi: incomplete constraints, leaving on
[    9.439105] Modules linked in: spidev(+) nvhost_vi
[    9.439421] [<c04127fc>] (driver_register+0x80/0x148) from [<bf00708c>] (spidev_init+0x8c/0xc0 [spidev])
[    9.439449] [<bf00708c>] (spidev_init+0x8c/0xc0 [spidev]) from [<c0008730>] (do_one_initcall+0xdc/0x198)

The problem just is that the chip-select enable, that is, going from 1.8V to 0V is going too slow. The message is already being transfered while the chip-select is still not ready as can be seen https://i.imgur.com/anM8h3K.png. I wonder how parameters can fix this?

You have define which GPIO pin as chipselect like below.
Find the correct GPIO pin and have your DT define like below.

spi@7000d600 {
    status = "okay";
 	spi@0 {
            nvidia,chipselect-gpio = <&gpio TEGRA_GPIO(S,4) 0>;

Hi ShaneCCC,

That seems to give an immediate syntax error when compiling with dtc:

Error: /boot/tegra124-jetson_tk1-pm375-000-c00-00.dts:2470.39-40 syntax error
FATAL ERROR: Unable to parse input tree

In general where is this documented? /usr/src/kernel/Documentation/devicetree/bindings/spi/nvidia,spi-tegra114.txt doesn’t specify this very precise, or I’m just to inexperienced.

edit:
ah this is supposed to go into the dtsi file. I still can’t get it to work properly though :( the chipselect is still discharging too slow. How can I figure out the correct bank and offset?

Here’s a snapshot of the 21.3 grinch linux kernel where spi is working correctly:

Here’s a snapshot of the 21.7 L4T where spi is not working correctly:

Could you help to compare the SPI driver for 21.3 with 21.7 to figure out the problem.

Hi Shane,

I’ll look into that, but could you first explain howto go from physical pin to TEGRA_GPIO()?

You need to include tegra-gpio.h for this define.

Yeah I understand, but my question is: What is the formula to go from TEGRA_GPIO(x,y) to physical pin? So what should x and y be for e.g. pin 6 on J3A1 at https://elinux.org/Jetson/GPIO

It’s GPIO3_PY.03, You can find it from pinmux table.
So it should be TEGRA_GPIO(Y, 3)