Run command: (this sample just send one byte)
root@nano: ./spidev_test -D /dev/spidev0.0 -s 1000000 -H -O -p “\x60”
My questions are:
How do I set SCK and MOSI to normal high?
How do I set or control CS timing? I set Jetson-Nano SPI CS active low, but why low too long, about 750us. As Figure1 show, when I send one byte, CS just need to 10us with clock 1MHz, but jetson-nano need to 750us~1000us?
After apply the patch, the CS still low too long, and these are my debug message.
attachment is my spi-tegra114.c
I trace the spi-tegra114.c code, I find the wait_for_completion_timeout() spend too long time.
Then I change the SPI_DMA_TIMEOUT value, still no effect.
Dec 17 10:15:51 will-desktop kernel: [ 78.925929] [drivers/spi/spidev.c] spidev_ioctl cmd=0x40046b05
Dec 17 10:15:51 will-desktop kernel: [ 78.925940] spidev spi0.0: setup 8 bpw, cpol, cpha, 1000000Hz
Dec 17 10:15:51 will-desktop kernel: [ 78.925983] spidev spi0.0: setup mode 3, 8 bits/w, 1000000 Hz max --> 0
Dec 17 10:15:51 will-desktop kernel: [ 78.925986] spidev spi0.0: spi mode 3
Dec 17 10:15:51 will-desktop kernel: [ 78.925990] [drivers/spi/spidev.c] spidev_ioctl cmd=0x80046b05
Dec 17 10:15:51 will-desktop kernel: [ 78.925994] [drivers/spi/spidev.c] spidev_ioctl cmd=0x40016b03
Dec 17 10:15:51 will-desktop kernel: [ 78.925999] spidev spi0.0: setup 8 bpw, cpol, cpha, 1000000Hz
Dec 17 10:15:51 will-desktop kernel: [ 78.926005] spidev spi0.0: setup mode 3, 8 bits/w, 1000000 Hz max --> 0
Dec 17 10:15:51 will-desktop kernel: [ 78.926008] spidev spi0.0: 8 bits per word
Dec 17 10:15:51 will-desktop kernel: [ 78.926012] [drivers/spi/spidev.c] spidev_ioctl cmd=0x80016b03
Dec 17 10:15:51 will-desktop kernel: [ 78.926015] [drivers/spi/spidev.c] spidev_ioctl cmd=0x40046b04
Dec 17 10:15:51 will-desktop kernel: [ 78.926019] spidev spi0.0: setup 8 bpw, cpol, cpha, 1000000Hz
Dec 17 10:15:51 will-desktop kernel: [ 78.926025] spidev spi0.0: setup mode 3, 8 bits/w, 1000000 Hz max --> 0
Dec 17 10:15:51 will-desktop kernel: [ 78.926028] [drivers/spi/spidev.c] spidev_ioctl cmd=0x80046b04
Dec 17 10:15:51 will-desktop kernel: [ 78.926204] [drivers/spi/spidev.c] spidev_ioctl cmd=0x40206b00
Dec 17 10:15:51 will-desktop kernel: [ 78.926215] [drivers/spi/spi-tegra114.c][tegra_spi_transfer_one_message][1437]
Dec 17 10:15:51 will-desktop kernel: [ 78.926219] [drivers/spi/spi-tegra114.c][tegra_spi_setup_transfer_one][1064]
Dec 17 10:15:51 will-desktop kernel: [ 78.926522] spi-tegra114 7000d400.spi: Setting clk_src clk_m
Dec 17 10:15:51 will-desktop kernel: [ 78.926554] [drivers/spi/spi-tegra114.c] cdata->is_hw_based_cs: 1
Dec 17 10:15:51 will-desktop kernel: [ 78.926556] [drivers/spi/spi-tegra114.c] cdata->cs_setup_clk_count: 3
Dec 17 10:15:51 will-desktop kernel: [ 78.926561] [drivers/spi/spi-tegra114.c] cdata->cs_hold_clk_count: 3
Dec 17 10:15:51 will-desktop kernel: [ 78.926565] [drivers/spi/spi-tegra114.c] cdata->rx_clk_tap_delay: 0
Dec 17 10:15:51 will-desktop kernel: [ 78.926570] [drivers/spi/spi-tegra114.c] cdata->tx_clk_tap_delay: 0
Dec 17 10:15:51 will-desktop kernel: [ 78.926573] [drivers/spi/spi-tegra114.c] cdata->cs_inactive_cycles: 0
Dec 17 10:15:51 will-desktop kernel: [ 78.926575] [drivers/spi/spi-tegra114.c] cdata->clk_delay_between_packets: 0
Dec 17 10:15:51 will-desktop kernel: [ 78.926588] [drivers/spi/spi-tegra114.c][tegra_spi_set_timing1][890]
Dec 17 10:15:51 will-desktop kernel: [ 78.926590] [drivers/spi/spi-tegra114.c] spi_cs_timing: 0
Dec 17 10:15:51 will-desktop kernel: [ 78.926592] [drivers/spi/spi-tegra114.c][tegra_spi_set_timing2][923]
Dec 17 10:15:51 will-desktop kernel: [ 78.926594] [drivers/spi/spi-tegra114.c] spi_cs_timing2: 538976288
Dec 17 10:15:51 will-desktop kernel: [ 78.926607] spi-tegra114 7000d400.spi: prod settings failed with error -19
Dec 17 10:15:51 will-desktop kernel: [ 78.926610] [drivers/spi/spi-tegra114.c][tegra_spi_start_transfer_one][1181]
Dec 17 10:15:51 will-desktop kernel: [ 78.926614] spi-tegra114 7000d400.spi: The def 0x47d08000 and written 0x73c01807
Dec 17 10:15:51 will-desktop kernel: [ 78.926617] [drivers/spi/spi-tegra114.c][tegra_spi_start_cpu_based_transfer][705]
Dec 17 10:15:51 will-desktop kernel: [ 78.926640] [drivers/spi/spi-tegra114.c] tspi->polling_mode: 0
Dec 17 10:15:51 will-desktop kernel: [ 78.926741] [drivers/spi/spi-tegra114.c] timeleft: 2500
Dec 17 10:15:51 will-desktop kernel: [ 78.926744] [drivers/spi/spi-tegra114.c] xfer->len: 2
Dec 17 10:15:51 will-desktop kernel: [ 78.926746] [drivers/spi/spi-tegra114.c] prefer_last_used_cs: 0
Dec 17 10:15:51 will-desktop kernel: [ 78.926748] [drivers/spi/spi-tegra114.c] complete_xfer 2
Dec 17 10:15:51 will-desktop kernel: [ 78.926751] [drivers/spi/spi-tegra114.c] xfer->cs_change: 0
Dec 17 10:15:51 will-desktop kernel: [ 78.926753] [drivers/spi/spi-tegra114.c] xfer->delay_usecs: 0
Dec 17 10:15:51 will-desktop kernel: [ 78.926755] [drivers/spi/spi-tegra114.c] cstate->cs_gpio_valid: 1
Dec 17 10:15:51 will-desktop kernel: [ 78.926757] [drivers/spi/spi-tegra114.c] spi->cs_gpio: 19
Dec 17 10:15:51 will-desktop kernel: [ 78.926760] [drivers/spi/spi-tegra114.c] complete_xfer 4
Dec 17 10:15:51 will-desktop kernel: [ 78.926762] [drivers/spi/spi-tegra114.c] prefer_last_used_cs: 0
Dec 17 10:15:51 will-desktop kernel: [ 78.926775] [drivers/spi/spi-tegra114.c] tspi->is_hw_based_cs: 1
I’m coming up against the same issue. The release of chip select is taking 200 - 1000 us after the transaction. I haven’t tried software CS yet or the patch, but I was hoping someone can confirm that this issue is being worked on.
Just an update. After running jetson_clocks.sh and making sure the Nano is set to max performance (even with 5W mode), the chip select is significantly faster to de-assert now (~50us). So this seems to be some sort of scheduling / response issue with the driver and the linux kernel.
It also seems that occasionally (1 in 20 transactions) the release happens a cycle (SCK) after the transaction is finished (extremely quickly) and the CS line is actually driven high (rise time is fast).
The remainder of the time when it takes 50us to deassert the CS line, the CS is released (ie. open drain) and is pulled high by the pull-up resistance.