Jetson Nano SPI access delay

Hello! On Channel 0 we’ve got the chip select, and Channel 4 is the clock.

We are running SPI at 2Mhz, but there seems to be a 400us delay between the chip select falling and rising again for the next transaction. This drastically reduces our ability to run SPI at 2Mhz. We have run jetson clocks and are running this on a jetson nano devkit.

Is there a way to reduce this time? We are using gpio chip selects, would this be characteristic of that? Are there any settings in the device tree we can use? In the IOCTL spi transfer we have the delay_usec set to 0.

Any help will be greatly appreciated.

Sorry for the late response, our team will do the investigation and provide suggestions soon. Thanks

Any update on this?

Looking into this. I will provide an update in few days

Can you share the dtb file ? is the hw cs property present in the device tree settings ?

device_tree.dts (330.5 KB)
here is the file we use

we don’t have hw cs property because we use cs-gpio

Any update on this?

@va11 @kayccc any updates on this?

@akhil.veeraghanta can you try using hw based CS instead of CS gpio?

We have, but the reason we are using CS gpio is because we need that SPI interface to handle 5 devices. With the hw based CS we only get 2