Hello! On Channel 0 we’ve got the chip select, and Channel 4 is the clock.
We are running SPI at 2Mhz, but there seems to be a 400us delay between the chip select falling and rising again for the next transaction. This drastically reduces our ability to run SPI at 2Mhz. We have run jetson clocks and are running this on a jetson nano devkit.
Is there a way to reduce this time? We are using gpio chip selects, would this be characteristic of that? Are there any settings in the device tree we can use? In the IOCTL spi transfer we have the delay_usec set to 0.