Hi,
I use the SPI of jetson to connect with a external ADC device. The ADS device support a 16khz sample rate, that is I should finish my read data stuff among 62.5us. I write a device driver, the core code as below
Thanks for you reply.
I think it may not be a clock issue.
I use a 5000000 Hz clock, I think it is fine for my need. The clock show as below. scope_0.bmp (1.2 MB)
But when I check the CS signal, I found after clock time, there is a long time to pull up CS signal, as follow. scope_7.bmp (1.2 MB)
Could you tell me how to reduce these time or How can I disable the CS . I can use gpio to simulate the CS signal.
Hi Shane, I check the changes in your patch and found the change has been merged in my version(32.5.1). Unfortunately, It seems still has trouble in CS delay.
Sorry for that Shane, I am new to the device driver. I don’t know how to config to use GPIO as CS, do I need to change the device tree or change the spi-tegra114.c?
And your method about adjust “nvidia,cs-hold-clk-count”,“nvidia,cs-inactive-cycles” , do you mean to add these items to dts file? And what value should I set for these item, where can I find the explain of these params.
I know it is boring to explain these to a freshman, so thanks a lot for your patient.
I mean I know how to use gpio to simulate as CS, I already use the gpio as CS in my project,but I don’t know how to config it for the spi directly.
However, for me, the problem is the CS delay time, so no matter about config gpio for SPI directly, I need only to reduce the SPI CS delay.
Thanks Shane, cause my driver do not use device tree, I write the spi related config code in the drvier directly, could you tell me how to adjust the “nvidia,cs-hold-clk-count”,“nvidia,cs-inactive-cycles” in the driver directly, and how to make