Jetson SPI communication time too long

I use the SPI of jetson to connect with a external ADC device. The ADS device support a 16khz sample rate, that is I should finish my read data stuff among 62.5us. I write a device driver, the core code as below

#include <linux/spi/spi.h>
int send_ad_cmd(u8 cmd)
{       int ret = -1;
        unsigned char txdata[1];
        txdata[0] = cmd;
        if( ads1299_device )
            struct spi_transfer	tr = 
                .tx_buf	= txdata,
                // .rx_buf = buf,
                .len		= 1,

            ret = spi_sync_transfer( ads1299_device, &tr, 1 );
        // ret = 0 , sync success
        return ret;

And I use the below code to test the time use SPI, the _RESET is a 1 byte data.

    gpio_set_value(ADS1299_CS_PIN, 0);
    gpio_set_value(ADS1299_CS_PIN, 1);

I test the code and use a Oscillograph to catch the time. I find it use ~160us.
The time is too long, how can I reduce the time in this process?

How about the SPI clock? Try modify the spi-max-frequency in dts

Thanks for you reply.
I think it may not be a clock issue.
I use a 5000000 Hz clock, I think it is fine for my need. The clock show as below.
scope_0.bmp (1.2 MB)
But when I check the CS signal, I found after clock time, there is a long time to pull up CS signal, as follow.
scope_7.bmp (1.2 MB)
Could you tell me how to reduce these time or How can I disable the CS . I can use gpio to simulate the CS signal.

I think I can put the image directly, and the green is clock, the yellow is CS

Hi Shane, I find a topic like my question, but I don’t know if this question has been solved.

This topic use the cs-gpio to adjust the cs gap but I didn’t verify it.

Thanks, do you have any other methods?

I can try this method. In this topic you modify this file
If I use jetson xavier agx, which file should I modify?

The same file with that.

Thanks, and then how to make this modification work? Should I compile the kernel and get which .ko file to jetson?

You need to modify and compile the kernel Image and replace it at /boot/Image

Thanks Shane, you mean use the or I can directly copy the Image file to /boot

You can just replace the Image instead of flash it.

Thanks Shane, I will try it.

Hi Shane, I check the changes in your patch and found the change has been merged in my version(32.5.1). Unfortunately, It seems still has trouble in CS delay.

Do you mean using GPIO as CS still the same?
Have a adjust the “nvidia,cs-hold-clk-count”,“nvidia,cs-inactive-cycles” … to check if any change?

Sorry for that Shane, I am new to the device driver. I don’t know how to config to use GPIO as CS, do I need to change the device tree or change the spi-tegra114.c?
And your method about adjust “nvidia,cs-hold-clk-count”,“nvidia,cs-inactive-cycles” , do you mean to add these items to dts file? And what value should I set for these item, where can I find the explain of these params.
I know it is boring to explain these to a freshman, so thanks a lot for your patient.

I mean I know how to use gpio to simulate as CS, I already use the gpio as CS in my project,but I don’t know how to config it for the spi directly.
However, for me, the problem is the CS delay time, so no matter about config gpio for SPI directly, I need only to reduce the SPI CS delay.

You need to add cs-gpios like below example.

spi@3210000 {
status = “okay”;
cs-gpios = <&tegra_main_gpio TEGRA194_MAIN_GPIO(C, 3) GPIO_ACTIVE_LOW>;

Thanks Shane, cause my driver do not use device tree, I write the spi related config code in the drvier directly, could you tell me how to adjust the “nvidia,cs-hold-clk-count”,“nvidia,cs-inactive-cycles” in the driver directly, and how to make

cs-gpios = <&tegra_main_gpio TEGRA194_MAIN_GPIO(C, 3) GPIO_ACTIVE_LOW>;

work in the driver directly.
Thanks a lot