By the help in this forum, I can put a small delay between packets in the SPI communication.
The test code sends 35 16-bit packets with 8-clock delay between them.
This is the patch I made:
---
.../t19x/jakku/kernel-dts/common/tegra194-p3668-common.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/nvidia/platform/t19x/jakku/kernel-dts/common/tegra194-p3668-common.dtsi b/nvidia/platform/t19x/jakku/kernel-dts/common/tegra194-p3668-common.dtsi
index 2b81267506b0..cc6c2305e688 100644
--- a/nvidia/platform/t19x/jakku/kernel-dts/common/tegra194-p3668-common.dtsi
+++ b/nvidia/platform/t19x/jakku/kernel-dts/common/tegra194-p3668-common.dtsi
@@ -416,6 +416,8 @@
spi@3210000{ /* SPI1 in 40 pin conn */
status = "okay";
+ num-cs = <1>;
+ cs-gpios = <&tegra_main_gpio TEGRA194_MAIN_GPIO(Z, 6) GPIO_ACTIVE_LOW>; /* from Jetson_Xavier_Nx_Pinmux_Configuration */
spi@0 { /* chip select 0 */
compatible = "spidev";
reg = <0x0>;
@@ -424,6 +426,7 @@
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
+ nvidia,cs-inactive-cycles = <0x08>;
};
};
spi@1 { /* chip select 1 */
What I want to do is to put the CS high(inactive) during the delay between packets.
Here is the desired CS pattern in the red line:
I read SPI_CS_TIMING2
in tegra_spi_start_transfer_one
function.
It reports 0x8 because it uses CS0 only. The CS doesn’t go high during the delay even I set it to 0x28. It doesn’t make any change if I set CS_ACTIVE_BETWEEN_PACKETS_0 to 0 or 1: