SPI Delay between words

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX2
1

I’m using the X2 as a spi master (controlling the SCLK) and I’m trying to get a small delay between every 8 bits of data sent. So every 8 clock cycles i want a minor delay. I dont want anything else to change (nothing to CS for example).

I previously misinterpreted the delay_usecs option in the spidev transfer to be the delay between words (words being defined by bits_per_word in the spidev transfer). After looking more intensely, it seems this is the delay for the full packet transfer.

I’m performer a spi transfer of 128 bytes with 8bits per word at 25MHz.

I see in the device tree the “nvidia,clk-delay-between-packets” option can be set to “the delay between “words”” which i hope is what i am looking for. Is that correct?

And also is there any way to update this value on a live system opposed to having to recompile the device table? I currently have a device remotely that i can’t flash a new kernel on.

Thanks in advance.

3

This device property was parser from the spi-tegra114.c driver. I think you can modify the driver to read it from file or debugfs or some where else.

4

I’ve pulled the spi114 driver out to be a ko so i can make edits.

Looking through the driver it seems this nvidia,clk-delay-between-packets settings requires GPIO CS. And we currently are using HW-CS i assume.

This statement fails:

if (cdata->cs_inactive_cycles || !cstate->cs_gpio_valid) {
	dev_err(&spi->dev,
		"Invalid cs packet delay config\n");
	tegra_spi_cleanup(spi);
	return -EINVAL;
}

How can i switch it to be “gpio” while not having to change the CS pin. Is that possible? Thanks.

5

There’s a note in kernel/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt

- nvidia,clk-delay-between-packets : Clock delay  between packets by keeping
  CS active. For this, it is required to pass the Chip select
  as GPIO.

spi@7000d400 { /* SPI 1 to 40 pin header */
      status = "okay";
      num-cs = <1>;
      cs-gpios = <&gpio TEGRA_GPIO(C, 3) GPIO_ACTIVE_LOW>;
      spi0_0 {
         #address-cells = <0x1>;
         #size-cells = <0x0>;
         compatible = "spidev";
         status = "okay";
         reg = <0>;
         spi-max-frequency = <54000000>;
         controller-data {
            nvidia,cs-setup-clk-count = <0x1e>;
            nvidia,cs-hold-clk-count = <0x1e>;
            nvidia,rx-clk-tap-delay = <0x1f>;
            nvidia,tx-clk-tap-delay = <0x0>;
         };
      };
   };