Hello All,
My SPI device requires the below thing:
Host should ensure that there is a delay of at least two SPI clocks between CS going low and start of SPI clock.
i.e. Minimum 2 SPI clock delay between CS active to rising edge of the first SPI
clock
How to configure this in Device Tree? Any method?
-Thanks.
1 Like
Have a reference to below topic to check if working for you.
The delay between between spi transfer and CS action is more than 100us(max up to 1ms), how to decease the delay time?
the device tree is below:
spi@7000d600 { /* SPI 2 to 40 pin header */
status = “okay”;
num-cs = <1>;
cs-gpios = <&gpio TEGRA_GPIO(B, 7) GPIO_ACTIVE_LOW>;
max3107spi@0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = “max3107_spi”;
status = “okay”;
reg = <0x0>;
spi-max-frequency = <25000000>;
controller-data {
nvidia,cs-setup-clk-count = <0>;
nvidia,cs-h…
1 Like
Hello ShaneCCC,
Checked this link. But it does not help.
Checked the 4 below registers:
Cmd 1 register
Cmd 2 register
Timing 1 register
Timing 2 register
But these registers settings does not help.
Please provide your inputs.
-Thanks.
Hello,
What is the use of these 2 parameters?
nvidia,cs-setup-clk-count =
nvidia,cs-hold-clk-count =
-Thanks.