SPI clocks delay between Chip select low and SPI clock

Hello All,
My SPI device requires the below thing:
Host should ensure that there is a delay of at least two SPI clocks between CS going low and start of SPI clock.
i.e. Minimum 2 SPI clock delay between CS active to rising edge of the first SPI
clock

How to configure this in Device Tree? Any method?

-Thanks.

1 Like

Have a reference to below topic to check if working for you.

1 Like

Hello ShaneCCC,
Checked this link. But it does not help.

Checked the 4 below registers:

  1. Cmd 1 register
  2. Cmd 2 register
  3. Timing 1 register
  4. Timing 2 register

But these registers settings does not help.

Please provide your inputs.

-Thanks.

Hello,
What is the use of these 2 parameters?

nvidia,cs-setup-clk-count =
nvidia,cs-hold-clk-count =

-Thanks.