I’m having an issue with the chip select timing with a Jetson Xavier on a custom board. I have a microcontroller connected to the jetson on spi0.0
The initial problem is that after the CS signal asserts the data from the Jetson was going out too quickly for our microcontroller to respond and the first byte wasn’t being properly read in from the microcontroller. I thought I addressed this issue by modifying the spi settings in the device tree by setting the nvidia,tx-clk-tap-delay = <25>;
After loading that custom device tree I can see the extra delay being applied, but only on the first spi transaction. The screenshot below shows a delay of 25us from when the CS goes low to when the clock starts.
However, on every subsequent transaction the delay between the CS and clk is significantly shorter and I’m back to seeing the first byte of my transmission lost.
Is there something I’m missing for the spi settings being overwritten?