SPI CS signal issue

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Xavier
,
1

Hi,
I use CS signal of SPI1 of xavier. But the CS signal could be pull down completely. The yellow line is CS signal.
scope_5.bmp (1.2 MB)
I do not know how to deal with it, so I choose use a gpio to replace the CS port.
The code of device tree is

	spi@3210000 {
		status = "okay";
		cs-gpios =<&tegra_aon_gpio TEGRA194_AON_GPIO(AA, 2) GPIO_ACTIVE_LOW>;
		ads1299@0 {
			compatible = "ads1299";
			reg = <0x0>;
			spi-max-frequency = <0x1f78a40>;

			controller-data {
				nvidia,cs-setup-clk-count = <0>;
				nvidia,cs-hold-clk-count = <0>;
				nvidia,rx-clk-tap-delay = <0>;
				nvidia,tx-clk-tap-delay = <0>;
			};
		};
		
	};

And I got the CS pull down well
scope_6.bmp (1.2 MB)

But when I contorl some property of spi_transfer

struct spi_transfer	tr = 
        {
            .tx_buf	= &t0,
            .len	= 1,
            .cs_change = 0,
            .delay_usecs = 2,
        };

The cs_change and the delay_usecs does not work, I need set a delay between a spi transfer , so now the situation does not solve my problem, could you give me some advice to deal with it?

2

I add the picture directly.
use spi cs0

image

use gpio250 as CS
image

5

We will investigate this issue and do the update soon. Thanks

6

Thank you kay, How can I check the update, will you notice me in at this topic?

7

@Gaosiy

Could you confirm change the compatible string in the device tree to “nvidia,tegra194-spi” this would enable the cs_active_delay_hw flag support.

8

Hi Shane, is this flag control the delay between to bytes in one spi transfer?
In my question,

struct spi_transfer	tr = 
        {
            .tx_buf	= &t0,
            .len	= 1,
            .cs_change = 0,
            .delay_usecs = 2,
        };

the delay_usecs did not work.

9

The cs_active_delay_hw should be the one define in device tree.

Have a check below property to trace the driver to figure it out.

Thanks

 	of_property_read_u32(data_np, "nvidia,cs-setup-clk-count",
1231  			     &cdata->cs_setup_clk_count);
1232  	of_property_read_u32(data_np, "nvidia,cs-hold-clk-count",
1233  			     &cdata->cs_hold_clk_count);
1234  	of_property_read_u32(data_np, "nvidia,rx-clk-tap-delay",
1235  			     &cdata->rx_clk_tap_delay);
1236  	of_property_read_u32(data_np, "nvidia,tx-clk-tap-delay",
1237  			     &cdata->tx_clk_tap_delay);
1238  	ret = of_property_read_u32(data_np, "nvidia,cs-inactive-cycles",
1239  				   &cdata->clk_delay_between_packets);
1240  	if (!ret)
1241  		cdata->is_cs_delay_inactive = 1;
1242  
1243  	/* clk_delay_between_packets is delay cycles active or inactive */
1244  	ret = of_property_read_u32(data_np, "nvidia,clk-delay-between-packets",
1245  				   &cdata->clk_delay_between_packets);
1246  	if (!ret)
1247  	/* is_cs_delay_inactive is used to decide cs active or inactive */
1248  		cdata->is_cs_delay_inactive = 0;
10

I know, I mean what is the function of this item, I found no related in the binding doc tegra114spi

11

Thanks Shane, by using this item, I have a delay between bytes.