I’ve been pulling my hair out trying to get the nvidia,clk_delay_between_packets, nvidia,cs_inactive_cycles, nvidia,cs-setup-clk-count and nvidia,cs-hold-clk-count spi slave attributes to work.
I finally got nvidia,cs-setup-clk-count and nvidia,cs-hold-clk-count to work so I can now set the time between CS going low and the clock starting, and the time between the clock stopping and the CS going high. This was only with the spi-tegra114.c patch in one of the other threads.
Getting nvidia,cs_inactive_cycles to work eluded me until I actually looked at the code. Here’s a snippet from tegra_spi_set_timing2.
if (!cdata || tspi->prod_list)
return;
if (!cdata->clk_delay_between_packets)
return;
if (cdata->cs_inactive_cycles) {
u32 inactive_cycles;
SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(spi_cs_timing2,
spi->chip_select,
Based on that code, cs_inactive_cycles is ignored if clk_delay_between_packets is NOT set.
OK, now look at this snippet from tegra_spi_setup.
if (cdata && cdata->clk_delay_between_packets) {
if (cdata->cs_inactive_cycles || !cstate->cs_gpio_valid) {
dev_err(&spi->dev,
"Invalid cs packet delay config\n");
tegra_spi_cleanup(spi);
return -EINVAL;
}
cdata->cs_inactive_cycles = cdata->clk_delay_between_packets;
}
According to that, clk_delay_between_packets and cs_inactive_cycles can’t both be set at the same time.
OK all clk_delay_between_packets does is set cs_inactive_cycles, so just set clk_delay_between_packets right? Unfortunately, setting clk_delay_between_packets requires that you use GPIOs for the chip selects. But if you use GPIOs for chip-selects, nvidia,cs-setup-clk-count and nvidia,cs-hold-clk-count no longer work. It’s also unclear just why clk_delay_between_packets can only be used with GPIO chip-selects since all it does it set cs_inactive_cycles. The work around is to either remove the check in tegra_spi_set_timing2 or remove the GPIO restriction in tegra_spi_setup.
Finally, I haven’t found any way to lower the time between transactions, only increase it. At 5MHz, with 8 bit words and only 1 byte in the transactions, the gap is a minimum of 48us. You can increase the gap using the “delay_usec” parameter on the write but that’s it. The gap seems to be somewhat proportional to the clock period but at 50MHz, the gap is still 32us and at 1HMz, the gap is about 108us. It doesn’t matter if it’s a PIO or DMA transfer. I’m guessing that the gap is a function of waiting for the transaction to complete or maybe a hardware restriction? Can someone from nvidia comment?