Jetson agx xavier having trouble booting

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Xavier
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Hello, I am modifying the device tree for spi communication on the jetson-agx-xavier-industrial custom board.

The L4T version is 35.4.1.

tegra194-soc-spi.dtsi was modified as follows.

spi0: spi@3210000 {
	compatible = "nvidia,tegra186-spi";
	reg = <0x0 0x03210000 0x0 0x10000>;
	interrupts = <0 36 0x04>;
	#address-cells = <1>;
	#size-cells = <0>;
	iommus = <&smmu TEGRA_SID_GPCDMA_0>;
	dma-coherent;
	dmas = <&gpcdma 15>, <&gpcdma 15>;
	dma-names = "rx", "tx";
	spi-max-frequency = <65000000>;
	nvidia,clk-parents = "pll_p", "clk_m";
	clocks = <&bpmp_clks TEGRA194_CLK_SPI1>,
		<&bpmp_clks TEGRA194_CLK_PLLP_OUT0>,
		<&bpmp_clks TEGRA194_CLK_CLK_M>;
	clock-names = "spi", "pll_p", "clk_m";
	resets = <&bpmp_resets TEGRA194_RESET_SPI1>;
	reset-names = "spi";
	status = "okay";
};

spi1: spi@c260000 {
	compatible = "nvidia,tegra186-spi";
	reg = <0x0 0x0c260000 0x0 0x10000>;
	interrupts = <0 37 0x04>;
	#address-cells = <1>;
	#size-cells = <0>;
	iommus = <&smmu TEGRA_SID_GPCDMA_0>;
	dma-coherent;
	dmas = <&gpcdma 16>, <&gpcdma 16>;
	dma-names = "rx", "tx";
	spi-max-frequency = <65000000>;
	nvidia,clk-parents = "pll_p", "osc";
	clocks = <&bpmp_clks TEGRA194_CLK_SPI2>,
		<&bpmp_clks TEGRA194_CLK_PLLAON>,
		<&bpmp_clks TEGRA194_CLK_OSC>;
	clock-names = "spi", "pll_p", "osc";
	resets = <&bpmp_resets TEGRA194_RESET_SPI2>;
	reset-names = "spi";
	status = "okay";
};

spi2: spi@3230000 {
	compatible = "nvidia,tegra186-spi";
	reg = <0x0 0x03230000 0x0 0x10000>;
	interrupts = <0 38 0x04>;
	#address-cells = <1>;
	#size-cells = <0>;
	iommus = <&smmu TEGRA_SID_GPCDMA_0>;
	dma-coherent;
	dmas = <&gpcdma 17>, <&gpcdma 17>;
	dma-names = "rx", "tx";
	spi-max-frequency = <65000000>;
	nvidia,clk-parents = "pll_p", "clk_m";
	clocks = <&bpmp_clks TEGRA194_CLK_SPI3>,
		<&bpmp_clks TEGRA194_CLK_PLLP_OUT0>,
		<&bpmp_clks TEGRA194_CLK_CLK_M>;
	clock-names = "spi", "pll_p", "clk_m";
	resets = <&bpmp_resets TEGRA194_RESET_SPI3>;
	reset-names = "spi";
	status = "okay";
};

The status of spi0, spi1, and sp2 to be used has been changed to okay, and the rest are in the default state.

In the case of tegra194-p2888-0001-p2822-0000-common.dtsi, it was written as follows.

spi@c260000 { /*SPI2 STM32*/
	compatible = "nvidia,tegra186-spi";
	status = "okay";
	num-cs = <1>;
	cs-gpios = <&tegra_main_gpio TEGRA194_MAIN_GPIO(C, 3) GPIO_ACTIVE_LOW>;
	
	spi@0 { /* chip select 0 */
		compatible = "tegra-spidev";
		reg = <0x0>;
		spi-max-frequency = <50000000>;
		controller-data {
			nvidia,enable-hw-based-cs;
			nvidia,rx-clk-tap-delay = <0x11>;
		};
	};
};

spi@3210000 { /*SPI1 HOLT*/
	compatible = "nvidia,tegra186-spi";
	status = "okay";
	num-cs = <1>;
	cs-gpios =<&tegra_main_gpio TEGRA194_MAIN_GPIO(Z, 6) GPIO_ACTIVE_LOW>;
	
	spi@0 { /* chip select 0 */
		compatible = "tegra-spidev";
		reg = <0x0>;
		spi-max-frequency = <50000000>;
		controller-data {
			nvidia,enable-hw-based-cs;
			nvidia,rx-clk-tap-delay = <0x11>;
		};
	};
};

spi@3230000 { /*SPI3 NVRAM*/
	compatible = "nvidia,tegra186-spi";
	status = "okay";
	num-cs = <1>;
	cs-gpios = <&tegra_main_gpio TEGRA194_MAIN_GPIO(Y, 3) GPIO_ACTIVE_LOW>;
	
	spi@0 { /* chip select 0 */
		compatible = "tegra-spidev";
		reg = <0x0>;
		spi-max-frequency = <50000000>;
		controller-data {
			nvidia,enable-hw-based-cs;
			nvidia,rx-clk-tap-delay = <0x11>;
		};
	};
};

spi@3270000 { 
	status = "disabled";
};

spi@3300000 {
	status = "disabled";
};

I know that I need to add the cs-gpios property, but if I define this property, it won’t boot. If I exclude this property, it will boot normally.

I am sharing my circuit diagram and pinmux.
In the case of pinmux, create a .cfg using the file extracted from the Excel spreadsheet and then enter the contents of the tegra19x-mb1-pinmux-p2888-0000-a00-p2822-0000-a00.cfg file under Linix_for_Tegra/bootloader/t186ref/BCT. Changed.

SPI3
SPI3784×121 12.1 KB

SPI2
SPI2795×145 12.2 KB

SPI3
SPI3868×133 14.4 KB

tegra19x-mb1-pinmux-p2888-0000-a00-p2822-0000-a00.txt (29.6 KB)

Attached is dmesg of booterror.
booterror.txt (78.8 KB)

3

Hi insu8897,

Running Set up redundant boot configuration: [   36.306187] rcu: INFO: rcu_preempt detected stalls on CPUs/tasks:
[   36.306557] rcu:     0-...0: (1 GPs behind) idle=d22/1/0x4000000000000000 softirq=528/529 fqs=2265
[   36.306865]  (detected by 2, t=5252 jiffies, g=133, q=54)
[   36.306981] Task dump for CPU 0:
[   36.307059] task:kworker/u16:1   state:R  running task     stack:    0 pid:   98 ppid:     2 flags:0x0000002a

From your boot up log, I can’t find the boot failed is caused from cs-gpios.

May I know what’s your requirement for SPI with AGX Xavier Industrial?
(i.e. which SPI interface you want to use? and which PIN is used for CS?)

Device tree will include other device tree files so that you don’t need to update the device tree like tegra194-soc-spi.dtsi. Or the configuration may be overwritten by other device tree overlay.

4

I also couldn’t find any logs in dmesg showing problems with cs-gpio and spi, so it’s difficult to debug.
The only thing I actually changed was the cs-gpios property.

In the case of SPI interface, jeson becomes the master for SPI1, 2, and 3, and for NVRAM, HOLT, and STM, all operate as slaves.

For CS PIN, use the same pin as Devkit and only use CS0.
SP1: SPI1_CS0_N (E55)
SP2: SPI2_CS0_N (D60)
SPI3: SPI3_CS0_N(C57)

If you use the basic pin like this, won’t it work if you just define the nvidia,enable-hw-based-cs property without specifying the gpio separately in cs-gpios?

controller-data {
nvidia,enable-hw-based-cs;
};

In the case of tegra194-soc-spi.dtsi, it was restored to its original state.
The situation hasn’t changed much.

5

It should work w/o defining cp-gpios since that hw based CS is configured by default.

Please try to remove cs-gpios property and perform loopback test by shorting MOSI and MISO and you can measure the behavior of CS pin (SPI1_CS0_N (E55) for SPI1).

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