Please review pinmux configuration to enable spi3

Hello, I am bringing up a jetson-agx-xavier-industrial custom board.

I enabled device-tree to communicate with the device connected to spi3, but the clock pin does not work.
(The cs pin was checked for operation with an oscilloscope.)

The schematic configuration is as follows:

The pinmux configuration is as follows.
pinmux_spi3.txt (31.0 KB)

Please confirm.

Hi insu8897,

pinmux.0x0243d008 = 0x00000000; # GPIO spi3_miso_py1
pinmux.0x0243d060 = 0x00000000; # GPIO spi3_mosi_py2
pinmux.0x0243d028 = 0x00000000; # GPIO spi3_cs1_py4
pinmux.0x0243d008 = 0x00001001; # spi3_miso_py1: rsvd1, tristate-disable, input-disable, io_high_voltage-disable, lpdr-disable
pinmux.0x0243d060 = 0x00001001; # spi3_mosi_py2: rsvd1, tristate-disable, input-disable, io_high_voltage-disable, lpdr-disable
pinmux.0x0243d028 = 0x00001001; # spi3_cs1_py4: rsvd1, tristate-disable, input-disable, io_high_voltage-disable, lpdr-disable
pinmux.0x0243d048 = 0x00001415; # spi3_sck_py0: rsvd1, pull-down, tristate-enable, input-disable, io_high_voltage-disable, lpdr-disable
pinmux.0x0243d018 = 0x00001415; # spi3_cs0_py3: rsvd1, pull-down, tristate-enable, input-disable, io_high_voltage-disable, lpdr-disable

It seems your pinmux is not configured for SPI usage correctly. (i.e. it is configured as GPIO currently)

Please configure them as following in pinmux spreadsheet.

@KevinFFF Thank you for answer.

As you mentioned, I modified pinmux using a spreadsheet.

However, as a result of checking the scope, only the signal from the CS pin is being caught.

Below is the changed PINMUX information.

change_pinmux.txt (29.7 KB)

Below is a picture of the scope, the yellow one is connected to the cs pin and the green one is clk.

Just in case, I will also share the device tree source.
Tegra194-p2888-0001-p2822-0000-common.dtsi

spi@c260000 { /*SPI2 STM32*/
	status = "okay";
	//num-cs = <1>;
	//cs-gpios = <&tegra_aon_gpio TEGRA194_AON_GPIO(CC, 3) 0>;
	
	spi@0 { /* chip select 0 */
		compatible = "tegra-spidev";
		reg = <0x0>;
		spi-max-frequency = <50000000>;
		controller-data {
			nvidia,enable-hw-based-cs;
			nvidia,rx-clk-tap-delay = <0x11>;
		};
	};
};

spi@3210000 { /*SPI1 HOLT*/
	status = "okay";
	//num-cs = <1>;
	//cs-gpios =<&tegra_main_gpio TEGRA194_MAIN_GPIO(Z, 6) 0>;
	
	spi@0 { /* chip select 0 */
		compatible = "tegra-spidev";
		reg = <0x0>;
		spi-max-frequency = <50000000>;
		controller-data {
			nvidia,enable-hw-based-cs;
			nvidia,rx-clk-tap-delay = <0x11>;
		};
	};
};

spi@3230000 { /*SPI3 NVRAM*/
	status = "okay";
	//num-cs = <1>;
	//cs-gpios = <&tegra_main_gpio TEGRA194_MAIN_GPIO(Y, 3) 0>;
	
	spi@0 { /* chip select 0 */
		compatible = "tegra-spidev";
		reg = <0x0>;
		spi-max-frequency = <50000000>;
		controller-data {
			nvidia,enable-hw-based-cs;
			nvidia,rx-clk-tap-delay = <0x11>;
		};
	};
};

It seems correct now.
Could you short MISO/MOSI together and perform loopback test through spidev_test?

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