dts file are as follows
spi@3230000{ /* SPI3 in 40 pin conn */
status = "okay";
num-cs = <8>;
cs-gpios = <&gpio TEGRA234_MAIN_GPIO(A, 6 ) GPIO_ACTIVE_LOW>,
<&gpio_aon TEGRA234_AON_GPIO(EE, 2) GPIO_ACTIVE_LOW>,
<&gpio TEGRA234_MAIN_GPIO(A, 5) GPIO_ACTIVE_LOW>,
<&gpio TEGRA234_MAIN_GPIO(Y, 4) GPIO_ACTIVE_LOW>,
<&gpio TEGRA234_MAIN_GPIO(E, 0) GPIO_ACTIVE_LOW>,
<&gpio TEGRA234_MAIN_GPIO(E, 1) GPIO_ACTIVE_LOW>,
<&gpio TEGRA234_MAIN_GPIO(E, 2) GPIO_ACTIVE_LOW>,
<&gpio TEGRA234_MAIN_GPIO(E, 3) GPIO_ACTIVE_LOW>;
spi@0 { /* chip select 0 */
compatible = "tegra-spidev";
reg = <0x0>;
spi-max-frequency = <50000000>;
controller-data {
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
spi@1 { /* chips select 1 */
compatible = "tegra-spidev";
reg = <0x1>;
spi-max-frequency = <50000000>;
controller-data {
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
spi@2 { /* chip select 2 */
compatible = "tegra-spidev";
reg = <0x2>;
spi-max-frequency = <50000000>;
controller-data {
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
spi@3 { /* chips select 3 */
compatible = "tegra-spidev";
reg = <0x3>;
spi-max-frequency = <50000000>;
controller-data {
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
spi@4 { /* chips select 4 */
compatible = "tegra-spidev";
reg = <0x4>;
spi-max-frequency = <50000000>;
controller-data {
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
spi@5 { /* chips select 5 */
compatible = "tegra-spidev";
reg = <0x5>;
spi-max-frequency = <50000000>;
controller-data {
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
spi@6 { /* chips select 6 */
compatible = "tegra-spidev";
reg = <0x6>;
spi-max-frequency = <50000000>;
controller-data {
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
spi@7 { /* chips select 7 */
compatible = "tegra-spidev";
reg = <0x7>;
spi-max-frequency = <50000000>;
controller-data {
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
};
Hi taylor_quan,
Are you using the devkit or custom board for AGX Xavier?
It seems you adding more pins as CS.
Which CS does not work in your case?
Have you tried using PIN24 of 40 pins expansion header as CS and configure it with hw based CS? (i.e. PZ.06)
system
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