I want to support SPI TPM module on AGX.
we do the setting as below
in <Linux_for_Tegra/source/kernel_src/kernel/kernel-5.10/arch/arm64/configs/defconfig>
after re-build and flash image .
the target hw board is the same.but
it can work well with Jetpack4.6.0 but fail in Jetpack5.0.2/5.1
in jetpack4.6.0 can appear /dev/tpm0
but in jetpack5.0.2/5.1 the /dev/tpm0 disappear and no /dev/spidev0.0 too.
Jetpack5.0.2/5.1 don’t support TPM module?
To make sure the modification in device tree takes effect. And can compare with device tree in Xavier/Jetpack 4.6 to make sure the setting is identical on the two releases.
Hi,
On Jetpack 5, certain setting is in dtbo file and probably it is not applied in device tree, so please boot to userspace and run xxd to inspect the device tree. To make sure it is same as Jetpack 4.
Little confused since you have said using tpm driver from 4.6 in 5.0.2. there is already driver in 5.0.2
We are also using the same tpm and it is working. But when we try to enable both tpm and spidev, in device tree the tpm fails. If we enable only tpm and disable spidev in device tree, then tpm works i.e., will appear as /dev/tpm0
Also please try using jetson-io.py and check. It may do some correct config which might make it work. We used it.
Once a fresh jetpack is installed, we followed the below steps on the Jetson
after configuring the kernel with the following configs
CONFIG_TCG_TPM=y
CONFIG_TCG_TIS_CORE=y
CONFIG_TCG_TIS_SPI=y
run “sudo /opt/nvidia/jetson-io/jetson-io.py” and configure the 40-pin header for SPI1 pins and then save.
use dtc to convert from dtb to dts the dtb file specified in FDT in /boot/extlinux/extlinux.conf
once converted to dts, update the following to the dts file
than you very much for your reply.
but may I know do your TPM work well on jetpack version 5.0.2/5.1 or just on jetpack4.6.x version ?
because our TPM can works well on jetpack4.6.x but fail on 5.0.2/5.1.
May I ask whether the TPM you use is SLB9670 or SLB9672?
Or is there a way to measure the behavior of the CS pin?
Because the problem we have is that when we use “nvidia,enable-hw-based-cs”, the behavior of the cs pin is not as required by SLB9672. We have confirmed this with Infineon’s FAE.
The waveforms we measured and the problems we encountered have opened another question on the following website, but no one has answered so far.