Hi Nvidia,
I’m tried to porting slb9670 on Orin NX 16GB and L4T35.2.1.
The slb9670 chip is connected SPI3 CS0.
I got error message and couldn’t find /dev/tpm0
sudo dmesg | grep spi
[ 14.697086] spi-tegra114 3210000.spi: Adding to iommu group 2
[ 14.745086] spi-tegra114 3230000.spi: Adding to iommu group 2
[ 14.789764] tpm_tis_spi: probe of spi2.0 failed with error -110
These is my pinmux and device tree.
pinmux:
spi3_sck_py0 {
nvidia,pins = "spi3_sck_py0";
nvidia,function = "spi3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
spi3_miso_py1 {
nvidia,pins = "spi3_miso_py1";
nvidia,function = "spi3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
spi3_mosi_py2 {
nvidia,pins = "spi3_mosi_py2";
nvidia,function = "spi3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
spi3_cs0_py3 {
nvidia,pins = "spi3_cs0_py3";
nvidia,function = "spi3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
spi3_cs1_py4 {
nvidia,pins = "spi3_cs1_py4";
nvidia,function = "spi3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
dtsi:
spi@3230000{ /* SPI3 in 40 pin conn */
status = "okay";
nvidia,clock-always-on;
cs-gpios = <&tegra_main_gpio TEGRA234_MAIN_GPIO(Y, 3) GPIO_ACTIVE_LOW>;
prod-settings {
#prod-cells = <3>;
prod {
prod = <0x04 0x0000003f 0x0f>;
};
};
slb9670@0{
compatible = "infineon,slb9670";
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <5000000>;
status = "okay";
//reset-gpios = <&tegra_main_gpio TEGRA194_MAIN_GPIO(S, 4) GPIO_ACTIVE_LOW>;
controller-data {
nvidia,variable-length-transfer;
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
};
I checked the spidev_test loopback is workd fine.
./spidev_test -v -D /dev/spi2.0
spi mode: 0x0
bits per word: 8
max speed: 500000 Hz (500 KHz)
TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D | ......@....?..................?.
RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D | ......@....?..................?.
The dtsi source code is work fine on the Xavier NX and JetPack 4.6.
But isn’t work on JetPack 5.
I have seen following post:
Maybe the prod-settings value is the key point or have other suggestions?