Hello everyone,
Since the Jetson Nano claims to provide CSI-2 v1.1 compliant ports, I made a custom board under the assumption that virtual channel support would be possible.
Unfortunately, even if virtual channels are a feature that has been present in the standard for a really long time, it is not present on the nano code base.
I’m not going to ask Nvidia to add support for this, since they have made it clear (on other posts) that there is no intention to do so.
I still want some official confirmation on whether it is possible to support virtual channels and what limitations does the system impose.
I would also appreciate any pointers regarding where to look on the code base.
I’m currently looking at vi2_fops.c and csi2_fops.c for clues on this matter.
Best Regards,
Juan Pablo.
hello juan.tettamanti,
please refer to Software Features,
virtual channel supports only enable for TX2 series, Xavier series, and NX series devices.
thanks
Hello @JerryChang,
Thanks for the info, but my question wasn’t about the supported software features.
It was about whether this can actually be supported by the hardware.
When you read the TX1 TRM on page 2273, it states that
A maximum of six data/pixel streams can be processed simultaneously at any given time.
The streams can come from any of the six possible sources, as shown below.
If the two streams come from a single source, then the streams are separated using a filter indexed on different virtual channel numbers or data types.
Also, if you check CSI_PIXEL_STREAM_A_CONTROL0_0 and CSI_PIXEL_STREAM_B_CONTROL0_0, you can see that both pixel parsers allow for selecting CSI interface A.
In addition, figure 116 on page 2274 also point in this direction
In conclusion, I wanted to know if the things mentioned in the manual are actually correct.
If the things on the datasheet are correct, do they apply exclusively to a 2-lane CSI configuration or can they also be used with a 4-lane CSI configuration?
It also bothers me that the Nano cannot handle something supported by smaller processors like the i.MX6 (Solo / Dual Lite / Dual / Quad) with it’s MIPI CSI-2 v1.0 (2005) interface.
Best Regards,
Juan Pablo.
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Hello @JerryChang,
Maybe I should have titled this “virtual channel support or equivalent”, since achieving a similar functionality through other means would not strictly be “virtual channel support”.
So reformulating my previous questions.
Would it be possible to use the pixel parsers to filter video from the same CSI interface with two different virtual channel ids?
Would that CSI interface be limited to using 2 lanes or can I also apply the filtering while using 4 lanes?
Best Regards,
Juan Pablo.
hello juan.tettamanti,
to clarify,
we’re using vc-id property in device tree to identify different streams,
however, Nano’s driver (i.e. vi2_fops.c and csi2_fops.c) did not have implementation to recognize that property,
if you’re interest,
you may look into TX2’s or Xavier’s kernel driver, searching for virtual_channel for more details.
you can enable 2-lane or 4-lane sensors on Nano, below camera combinations were supported
- three quad-lane camera streams, or
- two quad-lane plus two dual-lane camera streams, or
- one quad-lane plus three dual-lane camera streams.
please check Nano Product Design Guide, please refer to CSI connection session.
you may also look into Nano and NX Camera Design Guide for recommendations and guidelines of camera connectors.
thanks
Hello @juan.tettamanti,
Did you get any solution to use the CSI virtual channel on Jetson Nano? I have the same problem here, I made my carrier board with a video decoder IC, and it needs a MIPI virtual channel.
Hello @souzzalimma,
I spent some time on that and even got the pixel parsers to capture the video stream depending on the vc-id.
I got to the point where I could have two streams at the same time but it still wasn’t working correctly (don’t remember what was missing).
I’m not sure if your use case is the same as mine (two simultaneous streams), if your chip works like a mux (one stream at a time from N possible streams) or if it’s even more complex (N simultaneous streams).
Depending on the case, I might be able to remember something more or less useful.
I would still advice doing something else if you have the choice, since it will be much less painful.
Best Regards,
Juan Pablo.
Hello @juan.tettamanti,
Thanks for your reply. I need to use Nano, this a matter of cost. I’m using four CSI lanes, and the chip works like a mux from 4 streams. See below my application.
Hello @souzzalimma,
From what I see the NVP6324 is used for simultaneous streaming of the 4 available video sources and you ran into a similar problem than mine but worse.
The way I tried to get things to work was to get the two pixel parsers available to process one virtual channel each (since I only had two virtual channels).
With that in mind I changed the configuration of some registers like CSI_PIXEL_STREAM_A_CONTROL0_0 leaving most of the code untouched.
I do not know if it would be possible to extract the virtual channel id for each frame and go for a software solution here, since that would be different from what I originally explored.
You might still want to check if, for the same frame-rate and without any modifications, your frames come out properly sorted by pure luck.
Best Regards,
Juan Pablo.
