Jetson xavier nx Mipi data

Hi Nvidia,
we are getting raw frame from camera using v4l2 application and wanted to extract few details from Mipi receiver related to Mipi data.

I have following questions.
1.How to track the H-Blanking and V-Blanking of MIPI data. Is there a count maintained in the kernel, which can be accessed.
2.Are there any method to track the special packets for the frame start, frame end, line start, and line end information of mipi data? and also details about frame and line synchronization using which we can get frame number and line number details.

Do you have any suggestions can provide for our reference,
Thanks in advance.

hello ashwath.narasimhamurthy,

you should dump the NVCSI registers to obtain those details,
however, is it testing only? may I know the real use-case for checking them?

Hi JerryChang,

Thanks for the details. Sorry for late reply.

Is there any provision so that we can get interrupts for H-Blanking, V-Blanking, and also for special packets like frame start, frame end, line start, and line end etc. we so we can dump the NVCSI registers based on these interrupts.
Could you provide the details how to achieve this? We want to do it at kernel level not at application level.

Yes, internal and testing purpose only.

Use case is we are planning to bring up new camera sensor with Jeston Xavier nx platform and for testing purpose we need this real time data to be sure that sensor behavior is as expected with commercial MIPI receiver like Jetson Xavier nx.

Thanks,
Ashwath B N

hello ashwath.narasimhamurthy,

please download Xavier series TRM. usually, you may check the PH (packet head), PF (packet footer) of current packet.
for instance, NVCSI_STREAM_0_PH_WC_0, and NVCSI_STREAM_0_PF_CRC_0

FYI,
there’ll be error reported when the packet mismatch.
please refer to 7.2.2.2.2 CHANSEL of Notifications section (in page-1386) for more details. such as… PIXEL_SHORT_LINE, PIXEL_LONG_LINE…etc

here’s an example to dump CSI register for checking.

  1. please check TRM for [3.1.2 System Address Map] for the base address for NVCSI,
    for example, NVCSI 0x15a00000 0x15a4ffff SYSTEM
  2. please also check the register offset, NVCSI_STREAM_0_PH_WC_0, Byte Offset= 0x101dc
  3. calculate the address of PH_WC, i.e. 0x15a00000+0x101dc = 0x15a101dc
  4. please do enable the camera stream to dump the PH_WC for its register values,
    for example, $ sudo ./busybox devmem 0x15a101dc
    you should have such utility… $ sudo apt-get install busybox

Hi JerryChang,

Thanks for the information shared. we will go the Xavier series TRM.

The method you have suggested is to dump the registers and this is at application level. We want some method in kernel like getting interrupt and later read the required register at kernel level itself.
Dumping register value at application level will not serve our requirement. By the time application wants to dump the register for particular case, values of the register will be updated. If we read register at kernel level it will be real time value.

Thanks
Ashwath B N

Hi JerryChang,

Any update/information on this?

Thanks
Ashwath B N

hello ashwath.narasimhamurthy,

why don’t you add the code in kernel layer to dump the register values directly?

Hi JerryChang,

Yes, we can do that. Which all the interrupt we can tap it to achieve this?
If you can provide list of interrupts related to frame start, frame end, line start, and line end and for H-Blanking and V-Blanking it would be helpful.

In TRM mentions about start frame interrupt but doesn’t tell where to look in the code, hence checking with you on this regard.

Thanks
Ashwath B N

unfortunately, there’re only frame-start, frame-end through the code.
as you can see in the VI driver,
for instance, $public_sources/kernel_src/kernel/nvidia/drivers/media/platform/tegra/camera/vi/vi5_fops.c

static int tegra_channel_kthread_capture_enqueue()
{
                wait_event_interruptible(chan->start_wait,


static int tegra_channel_kthread_capture_dequeue()
{
                wait_event_interruptible(chan->dequeue_wait,