I am using both Jetson TX1 and Jetson TX2 with carrier board J120 as embedded computer to do my project without its fan.
There is problem that the computer burned up very fast when I ran streaming program. I checked process running board and found out that there are many processes but almost sleep, only my program running.
Anyone knows what factors lead to temperature going up ???
Thanks so much!
Hi AsleyTrung, have you consulted the Thermal Design Guides to inform an appropriate solution for passive cooling?
What clock rates are you running? What is the output of ~/tegrastats ?
My pleasure to meet you here.
Our concern is about services running on Jetson Tx1/Tx2.
I used gstreamer to run video streaming program at clock rate 90000. We use a lot of GPU for both encode H265 and image processing purposes.
And output tegrastats look like this:
Thanks so much !
From your tegrastats log, the CPU usage is ~70% (at 1734MHz) and GPU usage is up to 95%. So the processor is under load.
What cooling solution do you have on the J120?
Does it look like this? (CoolerMaster heatsink)
Or like this? (TTP - Thermal Transfer Plate)
If it looks like the bare TTP, you need airflow or to mount against a coldplate, as per the Thermal Design Guide.
FWIW, our TX2 runs much hotter with Auvidea J120 carrier board than with Nvidia DevKit board. Even at idle load with ambient temperature around 20C (with four out of six cores enabled and all clocks set to max) it needs fan to run to cool it down. The same setup running in DevKit board doesn’t require fan to be ON. I did try to disable all devices which we are not using in the device tree, but it didn’t help to make it run cooler. Not sure what is going on, but at this point I just take it as given. I would love to remove fan/heatsink to save weight, so if someone has any ideas, let us know.
We have a need to delid and backside thin the GPU processor IC for heavy ion SEE testing at TAMU cyclotron. Has anyone had experience with prepping the device for this type of test and had success with the modules functioning after thinning the backside silicon? Where can I get the mechanical dwgs for the TX1 and TX2 modules, the Tegra device bare die dimensional dwgs/specs and BOM of all collateral devices on the module CCA’s?