ok, tried without tweaking those eeprom sizes. flash went fine, but boot failed with below uart log:
[0000.095] W> RATCHET: MB1 binary ratchet value 4 is larger than ratchet level 2 from HW fuses. [0000.103] I> MB1 (prd-version: 220.127.116.11-t194-41334769-3540ffaa) [0000.108] I> Boot-mode: Coldboot [0000.111] I> Platform: Silicon [0000.114] I> Chip revision : A02P [0000.117] I> Bootrom patch version : 15 (correctly patched) [0000.122] I> ATE fuse revision : 0x200 [0000.126] I> Ram repair fuse : 0x0 [0000.129] I> Ram Code : 0x5 [0000.132] I> rst_source: 0x0, rst_level: 0x0 [0000.136] I> Boot-device: SDMMC (instance: 3) [0000.153] I> sdmmc DDR50 mode [0000.156] I> Boot chain mechanism: A/B [0000.160] I> Current Boot-Chain Slot: 0 [0000.164] W> No valid slot number is found in scratch register [0000.169] W> Return default slot: _a [0000.174] W> PROD_CONFIG: device prod data is empty in MB1 BCT. [0000.181] I> Temperature = 40500 [0000.185] W> Skipping boost for clk: BPMP_CPU_NIC [0000.189] W> Skipping boost for clk: BPMP_APB [0000.193] W> Skipping boost for clk: AXI_CBB [0000.197] W> Skipping boost for clk: AON_CPU_NIC [0000.201] W> Skipping boost for clk: CAN1 [0000.205] W> Skipping boost for clk: CAN2 [0000.209] I> Boot-device: SDMMC (instance: 3) [0000.218] I> Sdmmc: HS400 mode enabled [0000.222] I> Non-ECC region: Start:0x80000000, End:0x100000000 [0000.229] W> Thermal config not found in BCT [0000.237] W> MEMIO rail config not found in BCT [0000.260] I> sdmmc bdev is already initialized [0000.304] W> Platform config not found in BCT [0000.338] I> MB1 done ����main enter SPE VERSION #: R01.00.18 Created: Jan 29 2021 @ 14:18:27 HW Function test Start Scheduler. in late init �� [0000.347] I> Welcome to MB2(TBoot-BPMP) (version: default.t194-mobile-f46b967 3) [0000.348] I> DMA Heap @ [0x526fa000 - 0x52ffa000] [0000.348] I> Default Heap @ [0xd486400 - 0xd48a400] [0000.349] E> DEVICE_PROD: Invalid value data = 70020000, size = 0. [0000.355] W> device prod register failed [0000.359] I> Boot_device: SDMMC_BOOT instance: 3 [0000.363] I> sdmmc-3 params source = boot args [0000.369] I> sdmmc-3 params source = boot args [0000.372] I> sdmmc bdev is already initialized [0000.380] I> Found 21 partitions in SDMMC_BOOT (instance 3) [0000.386] I> Found 41 partitions in SDMMC_USER (instance 3) [0000.387] W> No valid slot number is found in scratch register [0000.392] W> Return default slot: _a [0000.396] I> Active Boot chain : 0 [0000.423] I> Relocating BR-BCT [0000.424] > DEVICE_PROD: device prod is not initialized. [0000.449] E> I2C: slave not found in slaves. [0000.450] E> I2C: Could not write 0 bytes to slave: 0x00ae with repeat start tr ue. [0000.451] E> I2C_DEV: Failed to send register address 0x00000000. [0000.452] E> I2C_DEV: Could not read 256 registers of size 1 from slave 0xae at 0x00000000 via instance 0. [0000.453] E> eeprom: Failed to read I2C slave device [0000.456] I> Failed to read CVB eeprom data @ AE [0000.460] I> Retrying CVB eeprom read @ AC ... [0000.465] E> I2C: slave not found in slaves. [0000.469] E> I2C: Could not write 0 bytes to slave: 0x00ac with repeat start tr ue. [0000.477] E> I2C_DEV: Failed to send register address 0x00000000. [0000.483] E> I2C_DEV: Could not read 256 registers of size 1 from slave 0xac at 0x00000000 via instance 0. [0000.492] E> eeprom: Failed to read I2C slave device [0000.496] I> Failed to read CVB eeprom data @ AC [0000.513] I> Relocating OP-TEE dtb from: 0x6bfff0f0 to 0x70050000, size: 703 [0000.514] I>  START: 0x80000000, SIZE: 0x2f000000 [0000.514] I>  START: 0xaf200000, SIZE: 0x18a00000 [0000.517] I> dram_block larger than 80000000 [0000.522] I>  START: 0x100000000, SIZE: 0xf80000000 [0000.529] I> Setting NS memory ranges to OP-TEE dtb finished. [0000.581] I> EKB detected (length: 0x410) @ VA:0x526ff400 [0000.582] I> Setting EKB blob info to OPTEE dtb finished. ��NOTICE: BL31: v2.5(release):ef8af0b99 NOTICE: BL31: Built : 11:45:39, Apr 6 2022 I/TC: �� ��I/TC: Non-secure external DT found ��bpmp: init bpmp: tag is 128431eec76692047e1ac1ebc0392266 sku_dt_init: not sku 0x00 clk_early initialized mail_early initialized fuse initialized hwwdt initialized t194_ec_get_ec_list: found 45 ecs ec initialized vmon_setup_monitors: found 3 monitors vmon initialized adc initialized fmon_populate_monitors: found 73 monitors fmon initialized mc initialized reset initialized nvhs initialized uphy_early initialized emc_early initialized ��I/TC: OP-TEE versi��392 clocks registered ��on: 6f444acf (gcc version 9.3.0 (Buildro��clk initialized ��ot��io_dpd initialized �� ��thermal initialized thermal_mrq initialized ��2020.08)) ��i2c initialized vrmon_dt_init: vrmon node not found vrmon_chk_boot_state: found 0 rail monitors vrmon initialized ��#2 Wed Apr 6 ��regulator initialized ��18:48:24 UTC 2022 aarch64 I/TC: Primary CPU initializing ��avfs_clk_platform initialized soctherm initialized aotag initialized powergate initialized dvs initialized pm initialized suspend initialized pg_late initialized pg_mrq_init initialized strap initialized nvl initialized emc initialized emc_mrq initialized clk_dt initialized tj_init initialized uphy_dt initialized uphy_mrq initialized uphy initialized ec_swd_poll_start: 281 reg polling start w period 47 ms ec_late initialized hwwdt_late initialized reset_mrq initialized ec_mrq initialized fmon_mrq initialized clk_mrq initialized avfs_mrq initialized mail_mrq initialized i2c_mrq initialized tag_mrq initialized console_mrq initialized mrq initialized clk_sync_fmon_post initialized ��I/TC: ��clk_dt_late initialized noc_late initialized ��Pr��pm_post initialized dbells initialized ��ima��dmce initialized cvc initialized ��ry CPU switching ��avfs_clk_mach_post initialized ��to n��avfs_clk_platform_post initialized ��orm��cvc_late initialized regulator_post initialized ��al w��rm initialized console_late initialized clk_dt_post initialized ��orl��mc_reg initialized ��d boot ��pg_post initialized profile initialized fuse_late initialized extras_post initialized bpmp: init complete entering main console loop ] �� Jetson UEFI firmware (version r34.1-975eef6 built on 2022-04-06T11:46:12-07: 00) ��ERROR: MPIDR 0x80000000: exception reason=0 syndrome=0xbe000000 Unhandled Exception in EL3. x30Unhandled Exception in EL3. x30
Please still set CVB size with 0. CVM should no need to be changed.
Just to confirm, we still need to set
eeprom.cvb_eeprom_read_size = 0 for both tegra194-mb1-bct-misc-flash.cfg and tegra194-mb1-bct-misc-l4t.cfg.
Yes, please try.
Was this board able to work if you set both eeprom read size to 0 in last time?
No, never worked, see my last comments in the last thread.
Which thread? I am asking about the original jp5.0DP without any overlay.
Was your board able to flash + boot up if you set both eeprom read size to 0 in that BSP?
If the board was not even boot up in that case, then it is different issue. Actually, your log looks like a different issue because MB2 already done. If this is same issue as previous one, then it shall got stuck in MB2 but not UEFI.
this is the post I had in the old thread that is already closed. I mentioned in that post the board didn’t come up even after modifying the files.
I just tried again after applying the overlay, and set
eeprom.cvb_eeprom_read_size = 0 for both tegra194-mb1-bct-misc-flash.cfg and tegra194-mb1-bct-misc-l4t.cfg and got the same error above.
Could you also set
eeprom.cvm_eeprom_read_size = 0 for your case and see if you can boot?
The log you just posted is different from what you hit last month. I feel these two are different issues.
Tried that, same error.
BTW, is that a way to flash everything except the APP partition? It takes a long time to push the system image to APP partition through the USB. Since we didn’t change anything in rootfs, it is a waste of time.
Is this still an issue to support? Any result can be shared? Thanks
I am working offline with neelp and cfritsch from nvidia team. We can close this.
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