I am using the flex parser(verilog.lex file) to parse a data file. The parsed data is sent to gpu for computation through fire_host.cu. Please note that lex.yy.c was compiling perfectly with gcc for the serial version of the same application.
all: output
output: lex.yy.c fire_host.cu
lex.yy.c: verilog.lex
clean:
However, on compiling I get an error:
line 681 in lex.yy.c corresponds to :#ifdef __cplusplus#else #endif
Please Help. I spent a lot of time on this but without any success !!!
–
I figured out what the problem was.
nvcc compiles in a c++ manner whereas flex does it in a C manner.
Hence there was some conflict with the variable names. Adding
extern “C” to all such functions removed all the problems. :)
I am using the flex parser(verilog.lex file) to parse a data file. The parsed data is sent to gpu for computation through fire_host.cu. Please note that lex.yy.c was compiling perfectly with gcc for the serial version of the same application.
This is my makefile:
all: output
output: lex.yy.c fire_host.cu
nvcc lex.yy.c fire_host.cu -o ESFF
lex.yy.c: verilog.lex
flex verilog.lex
clean:
rm -o ESFF
However, on compiling I get an error:
lex.yy.c(681): error: linkage specification is incompatible with previous “yywrap”
verilog.lex(23): here
line 681 in lex.yy.c corresponds to :
ifdef
static int yyinput (void );
else
static int input (void );
endif
Please Help. I spent a lot of time on this but without any success !!!
–
Warm Regards,
Dhruv Rastogi
5th yr EE, Dual Degree
IIT Madras