M.2 Key M (gen2 pcie x4) pinout

I would like to do a carrier board with an M.2 socket with the M key (gen2 pcie x4). Does anyone know how I might get the pinout for that socket? This seems to be a well kept secret at the moment. I have found only two ways so far:

  1. pay $4000 to join the pcie organization
  2. buy this https://www.amazon.com/gp/product/B00YT6YV3I/ref=oh_aui_detailpage_o00_s00?ie=UTF8&psc=1 and beep the pins, using the Jetson carrier board PCIe x4 as a key

This isn’t exactly the detail you are interested in, but this does have some outside URL references:

Note that pins which pass through other standards-compliant pins (such as PCIe or USB D+/D-) there shouldn’t be any difference between whether the pin is on an M.2 Key M board or a native version of the slot.

The publicly available diagrams show that the notched pins on the M key are 59-66. On the E key, these pins carry a second pex lane. M key probably has that lane where the E key is notched. The SD card pins are 9-23 on the odd side, that’s enough pins for another 2 pex lanes, which would be good because that makes all the PEX lines adjacent to each other for easy routing. I guess probably that’s where they go: odd side pins 9-55, broken up by grounds. But I have no way to know specifically how the signals map.

https://pcisig.com/specifications/order-form#Top of Order Form

These guys want $2,000 for a hard copy of the pinout. Is this the standard pathway to add an M.2 socket to my board?

Here is my schematic of the M.2 Key M. Does anyone have any advice or maybe they can correct a pin or two? I’m not sure where the I2C is supposed to connect. I feel like I am sure this is not quite right, but is pretty close.

Any updates on this?

I am working on a similar application and want to use PCI x4 capability on my carrier board.
I found the pinout information I in the document below in section 5.3 Pg19.


You must place coupling capacitors on the transmit lines.

They are placed per the carrier board schematic. 0.1uF. Is there anyting different that is required?

Not sure why SUSCLK is pulled up above, but in the spec, it is supposed to be a 32khz clock for low power modes. Not sure if its critical. Also, the SMBUS (i2c) lines need to be level shifted from 3.3 to 1.8v.

It appears that the SUCLK is an input by host but do not see that anywhere on Jetson. I got a PCIe to M2 adapter and it did not have that provided. Which would mean, I can live without the 32kHz clk input to the M2 hard drive.
Also, doesn’t seem like the M2 SSD needs SMBus per the design guide below. Check Pg 22.

Any inputs on I2C usage for SSD’s if using PCIe PHY?