Hi Nvidia Team,
Could you please guide us on how to add MCP 2515 can controller on Jetson Nano Emmc, we could enable the MCP 2515 on jetson nano Developer kit
I have shared the reference of the procedure which we have tried out to enable it on Jetson Nano Developer kit.
We are facing difficulty to enable it on Jetson Nano emmc module, if there is any dts file need to be loaded to use mcp 2515 on jetson nano Emmc please do share or any workaround.
Thank you
Please check below thread to see if can help: CAN with Jetson Nano Production Module - Jetson & Embedded Systems / Jetson Nano - NVIDIA Developer Forums
Hi ankithsingh,
maybe you have the same problem as I have.
I have a working CAN with the Jetson developer (SD-card) module, but it doesn’t work with the production (EMMC) module.
Reason seems to be configuration of the IO pins. I don’t have a solution yet. See link provided by kayccc.
Hi kayccc,
Spi pins are enabled and when i perform loopback testing it is performing well and showing me that spi pins are enabled on the emmc module, but unable to use CaN controller mcp-2515 if there is any dts file which need to be loaded please do share for the emmc version
Hi wri,
Any luck with the above query, could you able to resolve at your end?
Hi ankithsingh,
my problem was fixed with using JetPack 4.6.2 or 4.6.1.
The problem was that GPIOs were not configured the right way. You can check with
sudo cat /sys/kernel/debug/tegra_gpio
Line C must read something like
C: 0:2 00 00 00 00 00 00 000000
I suppose, that your problem is different from my problem, as your SPI works.
You can try
dmesg | grep spi
to see if can is listed.
Will check and let you know, what have you done in order to enable the Can on the nano emmc?
I made a special dtb, including
/ {
clocks {
can_clock: can_clock {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <20000000>;
clock-accuracy = <100>;
};
} ;
spi@7000d400 {
spi@0 {
status = "disabled";
};
spi@1 {
status = "disabled";
} ;
};
} ;
&spi0 {
/* avoid dtc warning */
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
can0: can@0 {
compatible = "microchip,mcp2515";
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(Z, 0) IRQ_TYPE_LEVEL_LOW>;
clocks = <&can_clock>;
nvidia,rx-clk-tap-delay = <0x7>;
nvidia,enable-hw-based-cs;
reg = <0x0>;
spi-max-frequency = <10000000>;
controller-data {
nvidia,cs-setup-clk-count = <0x1e>;
nvidia,cs-hold-clk-count = <0x1e>;
nvidia,rx-clk-tap-delay = <0x1f>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
};
I didn’t need to install any kernel module, as
mcp251x.ko
was already present in my installation under
/lib/modules/4.9.xxx-tegra/kernel/drivers/net/can/spi/
so this kernel module was already present while booting the emmc? and exactly in which dts file have you made the above changes? or whether you have created a new dts file? Thank you so much for help
Yes, the kernel module is part of standard L4T installation.
My dts is special, because it fits my custom made base board.
Maybe you will have to adapt the pinmux settings as well.
Hi could you guide me what exact changes need to be made in order to enable the can controller on the pinmux sheet because I couldn’t find any details related to can. Thank you
Good morning,
I understand that CAN is working on the developer version of Jetson Nano (the one with SD card) but not on emmc version. Correct?
Which version of L4t / JetPack are you using?
Have you checked the GPIO settings with
sudo cat /sys/kernel/debug/tegra_gpio?
Did you run
dmesg | grep spi
as proposed?
Hi wri,
I have tried the following on the latest jetpack this is the following output i am receiving.
Could you please let me know the patch which you have shared should it be added in any of the dtsi files before booting
Hi @ankithsingh,
this shows that your GPIO pins are configured correctly. So, your problem is different from the problem I had.
Also, SPI seems to be ok. (I use SPI@7000d400)
dmesg | grep SPI should include a line like this:
mcp251x spi0.0 can0: MCP2515 successfully initialized
It seems that CAN is not linked to this SPI in your device tree.
You should include the above mentioned code into your dts file and recompile the device tree. The generated .dtb should be copied to /boot and the dtb selected in /boot/extlinux/extlinux.conf.
Alternatively, you can also try to use jetson-io.
I didn’t use this, so I cannot help you a lot with this.
This thread may help you:
Jetson nano and mcp2515 can module - Jetson & Embedded Systems / Jetson Nano - NVIDIA Developer Forums
This is my output.
Pin connection
PIN 31 - INT
PIN 23 - SCK
PIN 24 - CS
PIN 19 - MOSI
PIN 21 - MISO
PIN 2 - VCC
GND - GND (PIN 25)
My pin connections are also correct
Ah, ok, there it is. CAN is known to the system and linked to SPI0.
Maybe, your pinmux setting is not correct.
This is discussed in detail in this thread:
CAN with Jetson Nano Production Module - Jetson & Embedded Systems / Jetson Nano - NVIDIA Developer Forums
Hi @wri
I followed the steps here is are the pinmux.dtsi and common.dtsi in which I have made the necessary changes please check if everything is okay as I have been trying since long. Thank you so much for your response
tegra210-porg-p3448-common.dtsi (21.7 KB)
tegra210-porg-pinmux-p3448-0000-b00.dtsi (38.2 KB)
Hi @wri
Could you please suggest any changes please
Hi @ankithsingh,
just returned from vacation and saw your post.
I can’t see a mistake in your files, but it is hard for me to debug your system from here. Also, I a m not really an expert in device tree - I am just happy that my system works after all.
I can suggest the following:
spi1_mosi_pc0 {
nvidia,pins = "spi1_mosi_pc0";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/ {
gpio: gpio@6000d000 {
gpio-init-names = "default";
gpio-init-0 = <&gpio_default>;
gpio_default: default {
gpio-input = <
TEGRA_GPIO(B, 4)
TEGRA_GPIO(B, 6)
TEGRA_GPIO(B, 7)
TEGRA_GPIO(DD, 0)
TEGRA_GPIO(S, 5)
TEGRA_GPIO(A, 5)
TEGRA_GPIO(X, 4)
TEGRA_GPIO(X, 5)
TEGRA_GPIO(X, 6)
TEGRA_GPIO(Y, 1)
TEGRA_GPIO(V, 1)
TEGRA_GPIO(Z, 0)
TEGRA_GPIO(Z, 2)
TEGRA_GPIO(J, 1)
TEGRA_GPIO(G, 0)
TEGRA_GPIO(G, 1)
TEGRA_GPIO(H, 2)
TEGRA_GPIO(H, 5)
TEGRA_GPIO(H, 6)
TEGRA_GPIO(I, 1)
TEGRA_GPIO(CC, 4)
>;
gpio-output-low = <
TEGRA_GPIO(S, 7)
TEGRA_GPIO(T, 0)
TEGRA_GPIO(Z, 3)
TEGRA_GPIO(H, 0)
TEGRA_GPIO(H, 3)
TEGRA_GPIO(H, 4)
TEGRA_GPIO(H, 7)
TEGRA_GPIO(I, 0)
TEGRA_GPIO(I, 2)
>;
gpio-output-high = <
TEGRA_GPIO(A, 6)
TEGRA_GPIO(X, 3)
TEGRA_GPIO(CC, 7)
>;
};
};
};
status="okay" ;