MCP 2518 FD CAN for Socket Can Interface

Hello,

I am trying to accomplish a socketCAN based interface on “ip link show” using 4 MCP2518 Modules and run 4 CAN buses on Nvidia Orin Nano. I am using Nvidia issued devboard without any mods.

Some info regarding project :

  • goal is control 16 motors via 4 can buses.
  • Added a custom PCB Board to Nvidia Orin Nano 40 pin header.
  • Custom PCB Contains 4 MCP2518FD for making 4 CAN Buses from Nvidia Orin Nano 40 pin header using 2 SPI uses CS0 and CS1 and utilizing 4 buses.
  • SocketCan/CAN Interface is required for cpp application to run on Nvidia Orin.
  • Currently only CAN 0 (built-in CAN controller) shows up in ip link show.
  • The expectation or goal is for “ip link show” to show 4 more can (SPI to CAN )interfaces in addition to CAN 0 which is built in controller on Nvidia Orin Nano Dev Board.
  • Downloaded & Flashed nvidia Jetson L4T 36.4(version matching my current NVIDIA orin) public sources.tbz2
  • MCP2518 Custom PCB Crystal is 20 Mhz right now.
  • Current ISR Pins on PCB (Please see attached screenshot) to recieve GPIO inputs.
  • Built the MCP2518 Module and then attached.
  • Having a hard time making final changes for enabling GPIO/Interrupt for SPI.

Attached screenshot shows these files
Board-Wired.jpg : picture of custom pcb
Board-TopDown.jpg : picture of custom pcb
mcp2518fd-overlay-try21.txt : overlay - able to add mcp node, but not without errors.
‘Module Attached.png’ : shows module attached to kernel
‘interrupt pins from mcp2518.png’ : 4 interrupt pins for 4 controllers
‘output when attaching module.png’ : grep output of dmesg when mcp2518fs module is loaded/probed.
live-running-dts-with-overlay-applied.txt : current DTS on kernel showing overlay changes were applied.

The process I am following for applying the device tree changes are

-convert the dts file to dtbo file
dtc -O dtb -o mcp2518fd-overlay.dtbo -@ mcp2518fd-overlay.dts

  • copy to boot
    sudo cp mcp2518fd-overlay.dtbo /boot

-configure to load at boot
sudo /opt/nvidia/jetson-io/config-by-hardware.py -n “MCP2518FD CAN Controllers”

  • update ifntramfs and reboot
    sudo update-initramfs -u

I am hoping if someone can guide me why is my overlay file producing errors and how do i enable these GPIO/Interrupt pins? is it also via overlay file??


any responses from anyone? i have been able to use esp32 and work with the custom pcb to establish the can bus connection, so custom pcb is not the problem.

all i am looking for is basically a right device tree that will let me bring up the socketcan/CAN interface?

any helpp?? or guidance??

Hi amoghjain,

Are you using the custom board for Orin Nano?
What’s the Jetpack version in use?

I would suggest you porting 2 MCP2518 module first and perform loopback test between them to verify first.
To port MCP2518 module on Orin Nano, you can refer to the following steps.

  1. enable kernel config
CONFIG_CAN_MCP251X=y
CONFIG_CAN_MCP251XFD=y
  1. device tree (modified them according to your actual connection).
    In tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi:
        clocks {
            // 20MHz external crystal oscillator
            clk20m: mcp251x_osc {
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency = <20000000>;
                clock-accuracy = <100>;
                clock-output-names = "mcp251x_clk20m";
            };
        };
..
        spi@3210000{ /* SPI0 */
            can@0 {
                compatible = "microchip,mcp251xfd";
                reg = <0x0>;
                interrupt-parent = <&gpio>; // Use the GPIO controller
                interrupts = <TEGRA234_MAIN_GPIO(Z, 7) IRQ_TYPE_LEVEL_LOW>; // GPIO3_PZ.07 is SPI0_CS1 for MCP2518 interrupt
                spi-max-frequency = <2000000>; // Set the max frequency to 2MHz
                clocks = <&clk20m>; // Use the 20MHz clock};
                nvidia,enable-hw-based-cs;
            };
        };

There’s a known SPI driver issue in JP6.
Please also apply Jetson orin nano SPI Speed not changing - #9 by KevinFFF to SPI master driver.