net/ DSA switch can`t work.

Autonomous Machines Jetson & Embedded Systems Jetson AGX Xavier
1

Hello

Where are the MDC and MDIO pins configured in device tree ? Or was it configured somewhere else?
I have replaced the original PHY chip with the Marvell 88E6352 chip now,the communication is not successful.

Thanks

2

Please refer to this thread.

https://devtalk.nvidia.com/default/topic/1050659/jetson-agx-xavier/xavier-ethernet-phy-chip-88e1512pb2-device-tree-file-/

3

I have already seen this topic ,and I configed

CONFIG_NET_DSA=y
CONFIG_NET_DSA_MV88E6XXX=y
CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y

my driver mv88e6085 has appears under /sys/bus/mdio_bus/drivers.
but the network still doesnt work . So ,how can I read the chips register data through MDIO?

Thanks

4

Please look at

TX2
hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-eqos.dtsi
Xavier
hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-platforms-eqos.dtsi

It is where brcm/Marvell PHY registers some information for eqos driver.

5

This is the original device tree

ether_qos@2490000 {
                /* PTP_ref clock speed in MHz */
                nvidia,ptp_ref_clock_speed = <312500000>;
                /* rxq_enable_ctrl = <rx0 rx1 rx2 rx3>
                 * 0x0 = Not enabled, 0x1 = Enabled for AV
                 * 0x2 = Enabled for Legacy, 0x3 = Reserved
                 */
                nvidia,rxq_enable_ctrl = <2 2 2 2>;
                nvidia,queue_prio = <0 1 2 3>;

                nvidia,use_tagged_ptp;
                nvidia,ptp_dma_ch = <3>;

                nvidia,chan_napi_quota = <64 64 64 64>;
                nvidia,pause_frames = <0>; /*0=enable, 1=disable */
                nvidia,phy-reset-gpio = <&tegra_main_gpio TEGRA194_MAIN_GPIO(G, 5) 0>;
                nvidia,phy-max-frame-size = <16>;       /* size in kbytes */
                nvidia,eth_iso_enable = <1>; /*0=enable, 1=disable */
                phy-mode = "rgmii-id";
                phy-handle = <&phy0>;

                mdio:mdio {
                        compatible = "nvidia,eqos-mdio";
                        #address-cells = <1>;
                        #size-cells = <0>;

                           phy0: ethernet-phy@0 {
                                reg = <0>;
                                interrupt-parent = <&tegra_main_gpio>;
                                interrupts = <TEGRA194_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
                                marvell,copper-mode;
                        };
                };
};

This is what I modified according to dsa.txt

ether_qos@2490000 {
                /* PTP_ref clock speed in MHz */
                nvidia,ptp_ref_clock_speed = <312500000>;
                /* rxq_enable_ctrl = <rx0 rx1 rx2 rx3>
                 * 0x0 = Not enabled, 0x1 = Enabled for AV
                 * 0x2 = Enabled for Legacy, 0x3 = Reserved
                 */
                nvidia,rxq_enable_ctrl = <2 2 2 2>;
                nvidia,queue_prio = <0 1 2 3>;

                nvidia,use_tagged_ptp;
                nvidia,ptp_dma_ch = <3>;

                nvidia,chan_napi_quota = <64 64 64 64>;
                nvidia,pause_frames = <0>; /*0=enable, 1=disable */
                nvidia,phy-reset-gpio = <&tegra_main_gpio TEGRA194_MAIN_GPIO(G, 5) 0>;
                nvidia,phy-max-frame-size = <16>;       /* size in kbytes */
                nvidia,eth_iso_enable = <1>; /*0=enable, 1=disable */
                phy-mode = "rgmii-id";
              phy-handle = <&switch0>;


                mdio {
                        compatible = "nvidia,eqos-mdio";
                        #address-cells = <1>;
                        #size-cells = <0>;

                        switch0: switch0@0 {
                                  compatible = "marvell,mv88e6352","marvell,mv88e6085";
                                  #address-cells = <1>;
                                #size-cells = <0>;
                                reg = <0>;

                                dsa,member = <0 0>;

                                ports {
                                        #address-cells = <1>;
                                        #size-cells = <0>;
                                        port@0 {
                                                reg = <0>;
                                                label = "lan0";
                                        };

                                        port@1 {
                                                reg = <1>;
                                                label = "lan1";
                                        };

                                        port@2 {
                                                reg = <2>;
                                                label = "lan2";
                                        };


                                   switch0port6:port@6 {
                                                reg = <6>;
                                                label = "cpu";
                                               // ethernet = <&fec1>;
                                             fixed-link {
                                                        speed = <100>;
                                                        full-duplex;
                                                };
                                        };
                        };
        };
};