MDIO bus not detecting PHY on custom AGX

We are trying to create a custom carrier for the AGX Xavier with a KSZ9897 switch chip connected to the RGMII/MDIO interface. We have found that the switch works independently from the AGX, but the PHY is not detected by the AGX’s MDIO bus, with the error “eth0: Could not attach to PHY” followed by “net eth0: eqos_open: Cannot attach to PHY (error: -19)” in the dmesg.

Our eqos device tree looks as follows:

ether_qos@2490000 {
compatible = “nvidia,eqos”;
reg = <0x00000000 0x02490000 0x00000000 0x00010000>;
reg-names = “eqos_base”;
interrupts = <0x00000000 0x000000c2 0x00000004 0x00000000 0x000000c3 0x00000004 0x00000000 0x000000be 0x00000004 0x00000000 0x000000ba 0x00000004 0x00000000 0x000000bf 0x00000004 0x00000000 0x000000bb 0x00000004 0x00000000 0x000000c0 0x00000004 0x00000000 0x000000bc 0x00000004 0x00000000 0x000000c1 0x00000004 0x00000000 0x000000bd 0x00000004>;
clocks = <0x00000004 0x00000120 0x00000004 0x00000020 0x00000004 0x00000022 0x00000004 0x00000021 0x00000004 0x00000023 0x00000004 0x00000008>;
clock-names = “pllrefe_vcoout”, “eqos_axi”, “eqos_rx”, “eqos_ptp_ref”, “eqos_tx”, “axi_cbb”;
resets = <0x00000005 0x00000011>;
reset-names = “eqos_rst”;
nvidia,local-mac-address = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
iommus = <0x00000002 0x00000014>;
iommu-group-id = <0x00000002>;
nvidia,csr_clock_speed = <0x00000019>;
nvidia,iso_bw = <0x00014000>;
nvidia,rx_riwt = <0x0000003c>;
nvidia,rx_frames = <0x00000010>;
nvidia,slot_intvl_val = <0x0000007c>;
status = “okay”;
pinctrl-names = “idle”, “default”;
pinctrl-0 = <0x0000001d>;
pinctrl-1 = <0x0000001e>;
nvidia,ptp_ref_clock_speed = <0x12a05f20>;
nvidia,rxq_enable_ctrl = <0x00000002 0x00000002 0x00000002 0x00000002>;
nvidia,queue_prio = <0x00000000 0x00000001 0x00000002 0x00000003>;
nvidia,ptp_dma_ch = <0x00000003>;
nvidia,chan_napi_quota = <0x00000040 0x00000040 0x00000040 0x00000040>;
nvidia,pause_frames = <0x00000001>;
nvidia,phy-reset-gpio = <0x00000013 0x00000035 0x00000000>;
nvidia,phy-max-frame-size = <0x00000010>;
nvidia,eth_iso_enable = <0x00000001>;
phy-mode = “rgmii-id”;
phy-handle = <0x0000001f>;
vddio_sys_enet_bias-supply = <0x00000020>;
vddio_enet-supply = <0x00000020>;
phy_vdd_1v8-supply = <0x00000021>;
phy_ovdd_rgmii-supply = <0x00000021>;
phy_pllvdd-supply = <0x00000020>;
linux,phandle = <0x000000bc>;
phandle = <0x000000bc>;
eqos-cool-dev {
cooling-min-state = <0x00000000>;
cooling-max-state = <0x00000005>;
#cooling-cells = <0x00000002>;
linux,phandle = <0x00000070>;
phandle = <0x00000070>;
prod-settings {
#prod-cells = <0x00000004>;
prod {
prod = <0x00000000 0x00008800 0x80000000 0x00000000 0x00000000 0x00008804 0x20000000 0x20000000>;
mdio {
compatible = “nvidia,eqos-mdio”;
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
ethernet-phy@0 {
reg = <0x00000000>;
phy_rst_lp_mode = <0x00000001>;
interrupt-parent = <0x00000013>;
interrupts = <0x00000034 0x00000008>;
marvell,reg-init = <0x00000003 0x00000012 0x00007fff 0x00000880>;
status = “okay”;
linux,phandle = <0x0000001f>;
phandle = <0x0000001f>;
fixed-link {
speed = <0x000003e8>;

Checking /sys/bus/mdio_bus/devices/, no devices are detected.

Do you have any documentation that will help us bring up this PHY? Thank you.

Have you followed the design guide to make the Ethernet part design? There are some guides and requests on the connections and layout routing. Have you already checked that well to make sure the HW is good?

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