No Display on DELL 27#monitor S2721QS with Jestson NX

L4T 32.6.1
Jetpack 4.6.1

Jetson NX SOM with our customization carrier board

Connect DELL 27# monitor S2721QS , no display after boot logo

SSH into system

user@linux:~$ xrandr --verbose
Screen 0: minimum 8 x 8, current 3840 x 2160, maximum 32767 x 32767
HDMI-0 connected primary 3840x2160+0+0 (0x145) normal (normal left inverted right x axis y axis) 600mm x 340mm
Identifier: 0x144
Timestamp: 7231
Subpixel: unknown
Gamma: 1.0:1.0:1.0
Brightness: 1.0
Clones:
CRTC: 0
CRTCs: 0
Transform: 1.000000 0.000000 0.000000
0.000000 1.000000 0.000000
0.000000 0.000000 1.000000
filter:
EDID:
00ffffffffffff0010ac97a14c554f30
211e0103803c2278ea5095a8544ea526
0f5054a54b00714f8180a9c0a940d1c0
e1000101010108e80030f2705a80b058
8a0055502100001e000000ff00364d44
393531330a2020202020000000fc0044
454c4c20533237323151530a000000fd
00283c82893c000a20202020202001b8
020345f1546101020304050607101112
1415161f20215d5e5f23090707830100
006d030c002000384420006003020167
d85dc401788001e40f010000681a0000
0101283ce6565e00a0a0a02950302035
0055502100001a000000000000000000
00000000000000000000000000000000
0000000000000000000000000000001e
TegraOverlayBlendmode: Opaque
supported: Opaque, SourceAlphaBlend, PremultSourceAlphaBlend
TegraOverlayPriority: 255
range: (0, 255)
BorderDimensions: 4
supported: 4
Border: 0 0 0 0
range: (0, 65535)
SignalFormat: TMDS
supported: TMDS
ConnectorType: HDMI
3840x2160 (0x14e) 594.177MHz +HSync +VSync +preferred
h: width 3840 start 4016 end 4104 total 4400 skew 0 clock 135.04KHz
v: height 2160 start 2168 end 2178 total 2250 clock 60.02Hz
3840x2160 (0x14f) 593.824MHz +HSync +VSync
h: width 3840 start 4016 end 4104 total 4400 skew 0 clock 134.96KHz
v: height 2160 start 2168 end 2178 total 2250 clock 59.98Hz
3840x2160 (0x145) 297.000MHz +HSync +VSync *current
h: width 3840 start 4016 end 4104 total 4400 skew 0 clock 67.50KHz
v: height 2160 start 2168 end 2178 total 2250 clock 30.00Hz
3840x2160 (0x151) 296.735MHz +HSync +VSync
h: width 3840 start 4016 end 4104 total 4400 skew 0 clock 67.44KHz
v: height 2160 start 2168 end 2178 total 2250 clock 29.97Hz
3840x2160 (0x152) 297.000MHz +HSync +VSync
h: width 3840 start 4896 end 4984 total 5280 skew 0 clock 56.25KHz
v: height 2160 start 2168 end 2178 total 2250 clock 25.00Hz
3840x2160 (0x153) 297.000MHz +HSync +VSync
h: width 3840 start 5116 end 5204 total 5500 skew 0 clock 54.00KHz
v: height 2160 start 2168 end 2178 total 2250 clock 24.00Hz
3840x2160 (0x154) 296.735MHz +HSync +VSync
h: width 3840 start 5116 end 5204 total 5500 skew 0 clock 53.95KHz
v: height 2160 start 2168 end 2178 total 2250 clock 23.98Hz
2560x1440 (0x18d) 241.545MHz +HSync -VSync
h: width 2560 start 2608 end 2640 total 2720 skew 0 clock 88.80KHz
v: height 1440 start 1443 end 1448 total 1481 clock 59.96Hz
2048x1280 (0x18e) 220.653MHz -HSync -VSync
h: width 2048 start 2190 end 2412 total 2776 skew 0 clock 79.49KHz
v: height 1280 start 1281 end 1284 total 1325 clock 59.99Hz
1920x1080 (0x155) 148.500MHz +HSync +VSync
h: width 1920 start 2008 end 2052 total 2200 skew 0 clock 67.50KHz
v: height 1080 start 1084 end 1089 total 1125 clock 60.00Hz
1920x1080 (0x156) 148.367MHz +HSync +VSync
h: width 1920 start 2008 end 2052 total 2200 skew 0 clock 67.44KHz
v: height 1080 start 1084 end 1089 total 1125 clock 59.95Hz
1920x1080 (0x157) 148.500MHz +HSync +VSync
h: width 1920 start 2448 end 2492 total 2640 skew 0 clock 56.25KHz
v: height 1080 start 1084 end 1089 total 1125 clock 50.00Hz
1920x1080 (0x15a) 74.250MHz +HSync +VSync
h: width 1920 start 2448 end 2492 total 2640 skew 0 clock 28.12KHz
v: height 1080 start 1084 end 1089 total 1125 clock 25.00Hz
1920x1080 (0x15b) 74.250MHz +HSync +VSync
h: width 1920 start 2558 end 2602 total 2750 skew 0 clock 27.00KHz
v: height 1080 start 1084 end 1089 total 1125 clock 24.00Hz
1920x1080 (0x15c) 74.178MHz +HSync +VSync
h: width 1920 start 2558 end 2602 total 2750 skew 0 clock 26.97KHz
v: height 1080 start 1084 end 1089 total 1125 clock 23.98Hz
1600x1200 (0x18f) 162.022MHz +HSync +VSync
h: width 1600 start 1664 end 1856 total 2160 skew 0 clock 75.01KHz
v: height 1200 start 1201 end 1204 total 1250 clock 60.01Hz
1600x900 (0x190) 108.003MHz +HSync +VSync
h: width 1600 start 1624 end 1704 total 1800 skew 0 clock 60.00KHz
v: height 900 start 901 end 904 total 1000 clock 60.00Hz
1280x1024 (0x191) 135.007MHz +HSync +VSync
h: width 1280 start 1296 end 1440 total 1688 skew 0 clock 79.98KHz
v: height 1024 start 1025 end 1028 total 1066 clock 75.03Hz
1280x1024 (0x15d) 107.968MHz +HSync +VSync
h: width 1280 start 1328 end 1440 total 1688 skew 0 clock 63.96KHz
v: height 1024 start 1025 end 1028 total 1066 clock 60.00Hz
1280x720 (0x15f) 74.250MHz +HSync +VSync
h: width 1280 start 1390 end 1430 total 1650 skew 0 clock 45.00KHz
v: height 720 start 725 end 730 total 750 clock 60.00Hz
1280x720 (0x160) 74.178MHz +HSync +VSync
h: width 1280 start 1390 end 1430 total 1650 skew 0 clock 44.96KHz
v: height 720 start 725 end 730 total 750 clock 59.94Hz
1152x864 (0x192) 108.003MHz +HSync +VSync
h: width 1152 start 1216 end 1344 total 1600 skew 0 clock 67.50KHz
v: height 864 start 865 end 868 total 900 clock 75.00Hz
1024x768 (0x193) 78.752MHz +HSync +VSync
h: width 1024 start 1040 end 1136 total 1312 skew 0 clock 60.02KHz
v: height 768 start 769 end 772 total 800 clock 75.03Hz
1024x768 (0x162) 65.002MHz -HSync -VSync
h: width 1024 start 1048 end 1184 total 1344 skew 0 clock 48.36KHz
v: height 768 start 771 end 777 total 806 clock 60.01Hz
800x600 (0x194) 49.500MHz +HSync +VSync
h: width 800 start 816 end 896 total 1056 skew 0 clock 46.88KHz
v: height 600 start 601 end 604 total 625 clock 75.00Hz
800x600 (0x163) 40.000MHz +HSync +VSync
h: width 800 start 840 end 968 total 1056 skew 0 clock 37.88KHz
v: height 600 start 601 end 605 total 628 clock 60.32Hz
720x576 (0x164) 27.000MHz -HSync -VSync
h: width 720 start 732 end 796 total 864 skew 0 clock 31.25KHz
v: height 576 start 581 end 586 total 625 clock 50.00Hz
720x480 (0x165) 27.000MHz -HSync -VSync
h: width 720 start 736 end 798 total 858 skew 0 clock 31.47KHz
v: height 480 start 489 end 495 total 525 clock 59.94Hz
720x400 (0x195) 26.171MHz -HSync -VSync
h: width 720 start 737 end 808 total 896 skew 0 clock 29.21KHz
v: height 400 start 401 end 404 total 417 clock 70.04Hz
640x480 (0x196) 31.500MHz -HSync -VSync
h: width 640 start 656 end 720 total 840 skew 0 clock 37.50KHz
v: height 480 start 481 end 484 total 500 clock 75.00Hz
640x480 (0x166) 25.174MHz -HSync -VSync
h: width 640 start 656 end 752 total 800 skew 0 clock 31.47KHz
v: height 480 start 490 end 492 total 525 clock 59.94Hz
DP-0 disconnected (normal left inverted right x axis y axis)
Identifier: 0x167
Timestamp: 7231
Subpixel: unknown
Clones:
CRTCs: 1
Transform: 1.000000 0.000000 0.000000
0.000000 1.000000 0.000000
0.000000 0.000000 1.000000
filter:
TegraOverlayBlendmode: Opaque
supported: Opaque, SourceAlphaBlend, PremultSourceAlphaBlend
TegraOverlayPriority: 255
range: (0, 255)
BorderDimensions: 4
supported: 4
Border: 0 0 0 0
range: (0, 65535)
SignalFormat: DisplayPort
supported: DisplayPort
ConnectorType: DisplayPort

user@linux:~$ xrandr --output HDMI-0 --mode 1920x1080 --rate 60.00
can display
user@linux:~$ xrandr --output HDMI-0 --mode 3840x2160 --rate 30.00
can display
user@linux:~$ xrandr --output HDMI-0 --mode 3840x2160 --rate 59.98
cannot display
user@linux:~$ xrandr --output HDMI-0 --mode 3840x2160 --rate 60.02
cannot display

we check the mode, this two-mode line seems not to conform with the CEA-861G (should be 594MHZ instead of 594.177, or 593.824)
, could you help explain fundamental why the NVIDIA Jeston display driver can not
the output that timming?

3840x2160 (0x14e) 594.177MHz +HSync +VSync +preferred
h: width 3840 start 4016 end 4104 total 4400 skew 0 clock 135.04KHz
v: height 2160 start 2168 end 2178 total 2250 clock 60.02Hz
3840x2160 (0x14f) 593.824MHz +HSync +VSync
h: width 3840 start 4016 end 4104 total 4400 skew 0 clock 134.96KHz
v: height 2160 start 2168 end 2178 total 2250 clock 59.98Hz


Can you use nv devkit to validate this issue?

sure, we can test it, stay tune , but i believe it will same , as we don’t change any HDMI TX part .

Interesting happen
we hae do more testing on 4K timming
user@linux:~$ xrandr --output HDMI-0 --mode 3840x2160 --rate 59.98
user@linux:~$ xrandr --output HDMI-0 --mode 3840x2160 --rate 60.02

  1. Cable A 1.5M no brand, devkit pass, our board fail

  2. Cable B 1M samzhe-1m devkit pass, our board pass

and we also testing use DP port , we found our DP port is pass.
any suggestion?

Sounds like not software issue. I don’t have suggestion. Maybe try to follow the tuning guide.

Thanks, i have some detail need ask,
if we tuning it ,how to apply make it persistence .

You need to put your parameters in the prod setting in the device tree.

Thanks, could you also provide the NX HDMI CDF file which we could use for ATC test? thanks

Sorry ,We don’t provide the CDF table here.

Hi. I found this setting in tegra194-p2888-0004-e3900-0000-common.dtsi files like:

	host1x {
		dpaux@155F0000 {
			status = "okay";
			compatible = "nvidia,tegra194-dpaux3-padctl";
			/delete-property/ power-domains;
			dpaux_default: pinmux@0 {
				dpaux3_pins {
					pins = "dpaux3-3";
					function = "i2c";
				};
			};

			prod-settings {
				prod_c_dpaux_dp {
					prod = <0x0 0x124 0x37fe 0xc001>;
				};
			};
		};
	};

But I don’t know how to add HDMI parameters, do you have an example?
Thanks.

No, not this prod-settings. It should be under hdmi-display.

			hdmi-display {
				compatible = "hdmi,display";
				status = "disabled";
				generic-infoframe-type = <0x87>;
				linux,phandle = <0x13e>;
				phandle = <0x13e>;

				disp-default-out {
					nvidia,out-type = <0x1>;
					nvidia,out-hotplug-state = <0x0>;
					nvidia,out-parent-clk = "pll_d";
					nvidia,out-xres = <0x1000>;
					nvidia,out-yres = <0x870>;
				};
			};

			prod-settings {
				#prod-cells = <4>;
				prod_list_hdmi_soc = "prod_c_hdmi_0m_54m","prod_c_hdmi_54m_111m","prod_c_hdmi_111m_223m","prod_c_hdmi_223m_300m","prod_c_hdmi_300m_600m";
				prod_c_dp {
					prod = <
						0 0x00000180 0x00000001 0x00000001		//SOR_NV_PDISP_SOR_DP_SPARE0_0	00:00=SEQ_ENABLE		0x1
						0 0x000005a4 0x0f0f0f00 0x05050300		//SOR_NV_PDISP_SOR_PLL0_0	27:24=ICHPMP			0x5
												//				19:16=FILTER			0x5
												//				11:08=VCOCAP			0x3
						0 0x000005a8 0x00000100 0x00000100		//SOR_NV_PDISP_SOR_PLL1_0	08:08=TMDS_TERM			0x1
						0 0x000005ac 0xf000ff00 0x00000000		//SOR_NV_PDISP_SOR_PLL2_0	31:28=PLL_MDIV			0x0
												//				15:08=PLL_NDIV			0x0
						0 0x000005b0 0x00000ff0 0x00000440		//SOR_NV_PDISP_SOR_PLL3_0	11:08=AVDD10_LEVEL		0x4
												//				07:04=AVDD14_LEVEL		0x4
						0 0x000005b4 0x00400000 0x00000000		//SOR_NV_PDISP_SOR_PLL4_0	22:22=ENB_LCKDET		0x0
						0 0x000005e4 0x00003b80 0x00001a00>;		//SOR_NV_PDISP_SOR_PLL5_0	13:11=PLL_SEL_TIMER		0x3
												//				09:07=PLL_LOCKDET2_SETUPN	0x4
				};
				prod_c_rbr {
					prod = <
						0 0x000005a8 0x00f00000 0x00200000>;		//SOR_NV_PDISP_SOR_PLL1_0	23:20=LOADADJ			0x2
				};
				prod_c_hbr {
					prod = <
						0 0x000005a8 0x00f00000 0x00200000>;		//SOR_NV_PDISP_SOR_PLL1_0	23:20=LOADADJ			0x2
				};
				prod_c_hbr2 {
					prod = <
						0 0x000005a8 0x00f00000 0x00300000>;		//SOR_NV_PDISP_SOR_PLL1_0	23:20=LOADADJ			0x3
				};
				prod_c_hbr3 {
					prod = <
						0 0x000005a8 0x00f00000 0x00300000>;		//SOR_NV_PDISP_SOR_PLL1_0	23:20=LOADADJ			0x3
				};
				prod_c_hdmi_0m_54m {
					prod = <
						0 0x000005a4 0x0f0f0f00 0x05050000              //SOR_NV_PDISP_SOR_PLL0
						0 0x000005a8 0x00f00100 0x00300100              //SOR_NV_PDISP_SOR_PLL1
						0 0x000005b0 0xff000ff0 0x38000440              //SOR_NV_PDISP_SOR_PLL3
						0 0x000005e4 0x00003f80 0x00002a00              //SOR_NV_PDISP_SOR_PLL5_0
						0 0x00000138 0xffffffff 0x333a3a3a              //SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0
						0 0x00000148 0xffffffff 0x00000000              //SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0
						0 0x000005b8 0x0040ff00 0x00400000>;            //SOR_NV_PDISP_SOR_DP_PADCTL0
				};
				prod_c_hdmi_54m_111m {
					prod = <
						0 0x000005a4 0x0f0f0f00 0x05050100              //SOR_NV_PDISP_SOR_PLL0
						0 0x000005a8 0x00f00100 0x00300100              //SOR_NV_PDISP_SOR_PLL1
						0 0x000005b0 0xff000ff0 0x38000440              //SOR_NV_PDISP_SOR_PLL3
						0 0x000005e4 0x00003f80 0x00002200              //SOR_NV_PDISP_SOR_PLL5_0
						0 0x00000138 0xffffffff 0x333a3a3a              //SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0
						0 0x00000148 0xffffffff 0x00000000              //SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0
						0 0x000005b8 0x0040ff00 0x00400000>;            //SOR_NV_PDISP_SOR_DP_PADCTL0
				};
				prod_c_hdmi_111m_223m {
					prod = <
						0 0x000005a4 0x0f0f0f00 0x05050300              //SOR_NV_PDISP_SOR_PLL0
						0 0x000005a8 0x00f00100 0x00300100              //SOR_NV_PDISP_SOR_PLL1
						0 0x000005b0 0xff000ff0 0x38000440              //SOR_NV_PDISP_SOR_PLL3
						0 0x000005e4 0x00003f80 0x00001a00              //SOR_NV_PDISP_SOR_PLL5_0
						0 0x00000138 0xffffffff 0x373a3a3a              //SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0
						0 0x00000148 0xffffffff 0x00000000              //SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0
						0 0x000005b8 0x0040ff00 0x00400000>;            //SOR_NV_PDISP_SOR_DP_PADCTL0
				};
				prod_c_hdmi_223m_300m {
					prod = <
						0 0x000005a4 0x0f0f0f00 0x05050300              //SOR_NV_PDISP_SOR_PLL0
						0 0x000005a8 0x00f00100 0x00300100              //SOR_NV_PDISP_SOR_PLL1
						0 0x000005b0 0xff000ff0 0x38000440              //SOR_NV_PDISP_SOR_PLL3
						0 0x000005e4 0x00003f80 0x00001a00              //SOR_NV_PDISP_SOR_PLL5_0
						0 0x00000138 0xffffffff 0x333d3d3d              //SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0
						0 0x00000148 0xffffffff 0x00000000              //SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0
						0 0x000005b8 0x0040ff00 0x00404000>;            //SOR_NV_PDISP_SOR_DP_PADCTL0
				};
				prod_c_hdmi_300m_600m {
					prod = <
						0 0x000005a4 0x0f0f0f00 0x05050300              //SOR_NV_PDISP_SOR_PLL0
						0 0x000005a8 0x00f00100 0x00300100              //SOR_NV_PDISP_SOR_PLL1
						0 0x000005b0 0xff000ff0 0x38000440              //SOR_NV_PDISP_SOR_PLL3
						0 0x000005e4 0x00003f80 0x00001a00              //SOR_NV_PDISP_SOR_PLL5_0
						0 0x00000138 0xffffffff 0x333d3d3d              //SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0
						0 0x00000148 0xffffffff 0x00000000              //SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0
						0 0x000005b8 0x0040ff00 0x00406000>;            //SOR_NV_PDISP_SOR_DP_PADCTL0
				};
			};
		};

is that all? how do i set it up?
Thank you very much!

I don’t know what is your exact problem. The registers are already there as a comment in the device tree.

  • There is 4 entry per prod configuration which are address_index, address _offset, mask, value.

This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.