No SPI Signals

I can’t there are other changes like pps and the pps input pin and adding the sd card that have been made in other files. These are lost if I use jetson_io.

What file causes these addresses? I changed disabled to okay in the 194 SPI (not at work so not sure of file name)

Add below 40pin configure to you device tree.

	pinmux@2430000 {
...
...
...
		header-40pin-pinmux {
			phandle = <0x179>;
			linux,phandle = <0x179>;

			pin37 {
				nvidia,lpdr = <0x0>;
				nvidia,io-high-voltage = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x1>;
				nvidia,pins = "spi3_mosi_py2";
				nvidia,function = "spi3";
			};

			pin28 {
				nvidia,lpdr = <0x1>;
				nvidia,io-high-voltage = <0x1>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x0>;
				nvidia,pins = "gen2_i2c_scl_pcc7";
				nvidia,function = "i2c2";
			};

			pin27 {
				nvidia,lpdr = <0x1>;
				nvidia,io-high-voltage = <0x1>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x0>;
				nvidia,pins = "gen2_i2c_sda_pdd0";
				nvidia,function = "i2c2";
			};

			pin26 {
				nvidia,lpdr = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x2>;
				nvidia,pins = "spi1_cs1_pz7";
				nvidia,function = "spi1";
			};

			pin24 {
				nvidia,lpdr = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x2>;
				nvidia,pins = "spi1_cs0_pz6";
				nvidia,function = "spi1";
			};

			pin23 {
				nvidia,lpdr = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x1>;
				nvidia,pins = "spi1_sck_pz3";
				nvidia,function = "spi1";
			};

			pin22 {
				nvidia,lpdr = <0x0>;
				nvidia,io-high-voltage = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x1>;
				nvidia,pins = "spi3_miso_py1";
				nvidia,function = "spi3";
			};

			pin21 {
				nvidia,lpdr = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x1>;
				nvidia,pins = "spi1_miso_pz4";
				nvidia,function = "spi1";
			};

			pin19 {
				nvidia,lpdr = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x1>;
				nvidia,pins = "spi1_mosi_pz5";
				nvidia,function = "spi1";
			};

			pin18 {
				nvidia,lpdr = <0x0>;
				nvidia,io-high-voltage = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x2>;
				nvidia,pins = "spi3_cs0_py3";
				nvidia,function = "spi3";
			};

			pin16 {
				nvidia,lpdr = <0x0>;
				nvidia,io-high-voltage = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x2>;
				nvidia,pins = "spi3_cs1_py4";
				nvidia,function = "spi3";
			};

			pin13 {
				nvidia,lpdr = <0x0>;
				nvidia,io-high-voltage = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x1>;
				nvidia,pins = "spi3_sck_py0";
				nvidia,function = "spi3";
			};

			pin10 {
				nvidia,lpdr = <0x0>;
				nvidia,io-high-voltage = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x1>;
				nvidia,pull = <0x2>;
				nvidia,pins = "uart1_rx_pr3";
				nvidia,function = "uarta";
			};

			pin8 {
				nvidia,lpdr = <0x0>;
				nvidia,io-high-voltage = <0x0>;
				nvidia,enable-input = <0x0>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x0>;
				nvidia,pins = "uart1_tx_pr2";
				nvidia,function = "uarta";
			};
		};

Where is that, what file. I have been editing dtsi for the SPI and pps.

It’s pinmux configure for SPI

Ok. What file does it go into, a dtsi or dts

Have reference to below topic.

I have the above in:
~/nvidia/nvidia_sdk/JetPack_4.6_Linux_JETSON_XAVIER_NX_TARGETS/Linux_for_Tegra/sources/hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-spi.dtsi

What I need to know is where do I put the pinmux that you gave me.

Thanks,

Add to in the pinmux@2430000{}

What file?

I think you should be able find it in the kernel sources.

The pinmux did not work (unless I put it in the wrong file), I get same pin register values for spi as I did before.

  • I added the header-40pin-pinmux to:
    ./nvidia_sdk/JetPack_4.6_Linux_JETSON_XAVIER_NX_TARGETS/Linux_for_Tegra/sources/hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi

  • then rebuilt:
    export CROSS_COMPILE=$HOME/nvidia/l4t-gcc/gcc-linaro-7.3.1-2018.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
    export CROSS_COMPILE=/home/asei/nvidia/l4t-gcc/gcc-linaro-7.3.1-2018.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
    export TEGRA_KERNEL_OUT=$HOME/nvidia/kernel_compiled
    export LOCALVERSION=-tegra
    cd ~/nvidia/nvidia_sdk/JetPack_4.6_Linux_JETSON_XAVIER_NX_TARGETS/Linux_for_Tegra/sources/kernel/kernel-4.9/
    make ARCH=arm64 O=$TEGRA_KERNEL_OUT -j2

  • move the files to correct place
    cd ~/nvidia/nvidia_sdk/JetPack_4.6_Linux_JETSON_XAVIER_NX_TARGETS/Linux_for_Tegra/kernel
    cp $TEGRA_KERNEL_OUT/arch/arm64/boot/Image Image
    cd dtb
    cp -a $TEGRA_KERNEL_OUT/arch/arm64/boot/dts/. .

  • Change to flash directory
    cd ~/nvidia/nvidia_sdk/JetPack_4.6_Linux_JETSON_XAVIER_NX_TARGETS/Linux_for_Tegra

  • Flash command
    sudo ./flash.sh -r -k kernel-dtb jetson-xavier-nx-devkit-emmc mmcblk0p1

  • I also tried
    sudo ./flash.sh -r jetson-xavier-nx-devkit-emmc mmcblk0p1

You can check if the dtb was applied by dmesg | grep -i kernel
Also confirm the context was add to dtb by using dtc to un-compile it to dts to confirm it.

There was no change in the inctrl_reg
The dtb file was loaded:
dmesg_grep_kernel.txt (1.6 KB)

here is the dts from the dtb., based on the pinctrl you gave me.
kernel_tegra194-p3668-all-p3509-0000.dts (256.3 KB)

Note:
If I use the jetson_io.py tool the pinctrl_reg look good.
There are differences in the dts files, but both have the pins defined but use different but similar names for the 40pin hdr.
kernel_tegra194-p3668-all-p3509-0000-user-custom.dts (254.4 KB)

Well, you can check the un-compile the dtb file to dts that generate by jetson-io to check if any different to clarify the problem.

Here is a dts generated by Jetson_io:
kernel_tegra194-p3668-all-p3509-0000-user-custom.dts (254.4 KB)

Here is the one using your 40 pin hdr:
kernel_tegra194-p3668-all-p3509-0000.dts (256.3 KB)

There are differnces in how the hdr is referenced, also a symbol is defined in the custom that is not in the other.

I copied the generated (custom) 40pin hdr into my spi dtsi file, It did not work either.

I will get that dto off the target and generate a dts and a custom dts.

When i use jetson_io I get the correct pinctrl_reg values.

Here is the DTS where I copied header-pinmux into my DTSI file then built the kernel.
kernel_tegra194-p3668-all-p3509-0000.dts (254.3 KB)

Here is the DTS using jetson_io:
kernel_tegra194-p3668-all-p3509-0000-user-custom.dts (254.4 KB)

Here are the two DTSI files I have changed for SPI.

tegra194-soc-base.dtsi (70.0 KB)

tegra194-soc-spi.dtsi (4.0 KB)

ShaneCCC Is there any information on why the SPI does not work when I add it via the tegra194-soc-spi.dtsi file?

I would suggest to configure it by jetson-io then extract it by “sudo dtc -I fs -O dts -o extracted_proc.dts /proc/device-tree” and add customized context to the extracted_proc.dts and compile it to dtb by dtc

That really does not fix the problem of not generating a working DTB from the SPI DTSI file, just goes around it.

I didn’t figure out the root cause now.
Please modify below cfg file to correct value and reflash the device by sudo ./flash.sh -r jetson-xavier-nx-devkit-xxx mmcblk0p1 to verify it.

../JetPack_4.6_Linux_JETSON_XAVIER_NX_TARGETS/Linux_for_Tegra/bootloader$ find -name tegra19x-mb1-pinmux-p3668-a01.cfg