NVIDIA Tegra X1 Mobile Processor - Video Input queries

Hi,

I have following queries on NVIDIA tegrax1 Video Input interface, please help me out!!

  1. The Video Input can be configured to capture various input format and dump the captured data in to the memory directly without using ISP. Now the format of the input data can be configured in VI_CSI_0_CSI_IMAGE_DT_0 register and output format in VI_CSI_0_IMAGE_DEF_0. The section 31.3.4 “YUV Pixel Data Formatting” in TRM says that the output of VI can be dumped in “YUV420 8-bit legacy” and “YUV420 8-bit /8-bit (CSPS)” format. What exactly are these formats? Are these formats same as standard NV12 format?

  2. The register VI_CSI_0_SURFACE0_OFFSET_MSB_0 used for programming the Memory address is double buffered. Does it mean that there is a FIFO of depth two and two different set of memory addresses can be programmed immediately one after the other and will take effect on two different single shot update? The VI description mentions that these are shadow registers and shall be copied on next EOF to actual registers. Is VI_CSI_0_SURFACE0_OFFSET_MSB_0 a shadow regiter?

Thanks in advance.

Regards,
Prasad.

Hi MallyaPrasad
You may get the detail information from the csi-2 spic.