Orin MGBE XFI port connect to switch 88q6113

Hi, all:
we are debuging our custom board. In our costom board, the MGBE port is directly connnct to our switch 88q6113, just show as below.

on hareware we set the the port as 10GBASE-R

on software, I follow the instruction below


modify the MGBE dt as below

/ {
	/* MGBE - A */
	ethernet@6810000 {
		status = "okay";
		nvidia,mac-addr-idx = <1>;
		/* 0=enable, 1=disable */
		nvidia,pause_frames = <0>;
		phy-mode = "10gbase-r";
		/* 1:10G, 0:5G */
		nvidia,uphy-gbe-mode = <1>;
		/* 0:XFI 10G, 1:XFI 5G, 2:USXGMII 10G, 3:USXGMII 5G */
		nvidia,phy-iface-mode = <0>;
		nvidia,max-platform-mtu = <16383>;
		fixed-link {
				speed = <10000>;

when the system setup, I get dmesg as below.

nvidia@tegra-ubuntu:~$ sudo dmesg | grep 681
[    6.681009] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
[   12.243876] nvethernet 6810000.ethernet: Adding to iommu group 52
[   12.250446] nvethernet 6810000.ethernet: failed to read skip mac reset flag, default 0
[   12.258632] nvethernet 6810000.ethernet: failed to read MDIO address
[   12.265211] nvethernet 6810000.ethernet: setting to default DMA bit mask
[   12.272905] nvethernet 6810000.ethernet: failed to get phy reset gpio error: -2
[   12.285153] nvethernet 6810000.ethernet: Ethernet MAC address: 48:b0:2d:78:9b:b1
[   12.293099] nvethernet 6810000.ethernet: Macsec not enabled
[   12.298848] nvethernet 6810000.ethernet: Macsec: Reduced MTU: 1466 Max: 16383
[   12.308199] nvethernet 6810000.ethernet: eth1 (HW ver: 31) created with 10 DMA channels

here the detail dmesg

eth_dmesg.log (69.6 KB)

now the question is on the orin side

ethtool eth1

show the Link detected: no

so any suggestion about this issue, thx

Hi, did you follow the Design Guide as below to make your design? You schematic seems not follow the DG, please share your full MGBE part schematic for check.

hi, Trumany
thank you for your reply. In fact our orin didn’t use a 10g phy, it’s UPHY_TX/RX6 are directly connect to the switch port. the block diagram as follow

What is the REFCLK connection in your design?

here’s the sch

Got it, why do you not use MDIO of Orin? Is it validated before?

our hardware enginner design similar sch for orin on other company , and it has test that the design can work.


Please refer to the check from the adaptation guide first.

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