Orin Nano : 3V3 I2C to 1V8 I2C


Currently we are designing a custom carrier board for Jetson Orin Nano.
I need two separate I2C bus running at 1V8.
Jetson Orin Nano has one bus available at 1V8 (I2C2) , but rest of them are 3V3 and thus I need to level shift.
Jetson Orin Nano Datasheet Section 4.3 Digital Logic specifies the max VOL for I2C0 and I2C1 as 0.3*VDD = 0.99V. This VOL is so high that bi-directional level shifter such as TXS0102 (max VIL = 0.15V) will not work.

What are the recommended IC / methods to level shift I2C from 3V3 to 1V8 ?

AGX Orin has the same specifications. NVidia uses this levelshifter on the AGX Orin Devkit Carrier:


This IC is used for 1V8 → 3V3 translation in the Orin AGX carrier board, and since the SoC is on the 1V8 rail, the max VOL is lower than Orin Nano ( 0.54V vs 0.99V) .

However, now looking at the Orin AGX carrier board design, I have additional question for the I2C level shifter implementation.

Jetson Orin AGX Datasheet says the max VOL for open drain, I2C pin of the module is 0.3 * VDD = 0.54V. On the Orin AGX Design sheet it says all I2C have 1kR internal pullup to 1.8V on the module.

The level shifter IC used on the carrier board , FXMA2102, has max VIL of 0.4V.
Since VOL> VIL , there is a chance for the level shifter to enter undefined state.

Additionally, the I2C specification mandates a maximum VOL of 0.4V (for IOL = 3mA. which is what is claimed on AGX datasheet) which the value of VOL on Orin AGX or Orin Nano exceeds.

Is there an error in the datasheet specification for VOL?
Or am I misunderstanding something here?

Hi, we are checking this, will update once available, thanks.

Hi, please refer to below answers:

  1. Levelshifter FXMA2102 (or TXS0102) are using pass-gate architecture. For FXMA2102, the Vil in datasheet is given with some conditions. As I2C spec shows, VoL = 0.4V, it needs to ensure Vol is within 0.4V. So Vil = 0.4V – voltage drop across the pass-gate. In other words, I2C levelshifter with such architecture will most likely show Vil < 0.4V.
  2. It depends on our internal driving setting. Our internal pull down res is around 50 ohm. So no matter 0.2VDD or 0.4 V, it will meet spec.


I don’t have issue with the FXMA2102 VIL specification.
VIL < 0.4V satisfies the I2C spec (assuming the VOL of the transmitter is max 0.4V) and thus the specification for this IC makes sense to me.

What I am confused is the specification of VOL for I2C ports given on Orin Nano / Orin AGX.
Again, the VOL is specified as 0.3VDD for I2C output low which is 0.54V for pullup with 1V8 (Orin AGX) , and 0.99V for pullup with 3V3 (Orin Nano). Both of these values are higher than the I2C VOL spec of 0.4V.

Additionally, what do you mean by the internal pulldown resistor ? I2C is open drain configuration so it shouldn’t have internal pulldown enabled.

The Vol needs to be tuned accordingly if necessary. The VDD is the internal pin supply which is 1.2V or 1.8V. The real Vol value= internal pull down res * Iol. The internal pull down can be tuned so as to fulfill the Vol of I2C spec. In fact, the current default value can fulfill the I2C spec.


Regarding the VDD, I have asked it in this post before and was told the VDD is the external pull-up voltage (for Orin Nano 3V3 rather than 1V8 which is the internal pin supply). For final confirmation, which supply does the I2C pin reference ?

Also if I am understanding what you are saying correctly, the open drain pin type can also configure the drive strength similar to push-pull pins? And as you said those are typically 50 ohm, but what is the minimum and maximum?

I had updated that post based on latest information got.

Yes, the drive strength can be configured. We don’t share the range, but it is 50 ohm typically.

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