Dear Nvidia Team,
We have designed a carrier board for Orin nx. The Rest of Orin nx is bidirectional and 1.8V signal. But in our carrier board we have use voltage level translator to convert from 1.8V to 3.3V signal. But when the reset signal is connected to the level translator, the reset is always low and objecting the successful boot of the device. But when i leave the reset floating (connected to nothing), the reset will go high and orin nx successfully boots. The level translator used is TXB0302DQMR.
What might be the reason for reset going low when it is connected…?
Regards,
Venkat.
*** Please note that this reply is generated by LLM automatically ***
The issue you’re experiencing with the reset signal going low when connected to the level translator (TXB0302DQMR) and preventing the successful boot of the Orin NX device is likely due to the way the level translator is configured or the characteristics of the translator itself.
Here are a few possible reasons for this behavior:
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Pull-down or pull-up configuration: The TXB0302DQMR level translator has internal pull-up and pull-down resistors that can be enabled or disabled depending on the configuration. If the pull-down resistor is enabled on the output side of the translator, it could be pulling the reset signal low, preventing the device from booting. Check the configuration of the level translator to ensure that the pull-down resistor is not enabled.
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Voltage level translation: The TXB0302DQMR level translator is designed to translate voltage levels between 1.8V and 3.3V. However, in your case, you’re trying to translate from 18V to 3.3V, which is outside the recommended operating range of the translator. This could be causing the translator to malfunction or not function as expected, resulting in the reset signal going low.
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Input impedance: The input impedance of the level translator might be too low, causing the reset signal to be pulled low. Check the input impedance of the translator and ensure that it’s compatible with the output impedance of the Orin NX device.
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Capacitive loading: The level translator might be introducing capacitive loading on the reset signal, causing it to be pulled low. Check the capacitive loading of the translator and ensure that it’s within the recommended limits.
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Signal integrity: The signal integrity of the reset signal might be compromised due to the level translator, causing it to be pulled low. Check the signal integrity of the reset signal and ensure that it’s within the recommended limits.
To resolve this issue, you could try the following:
- Use a different level translator: Consider using a level translator that’s specifically designed for translating voltage levels between 18V and 3.3V.
- Configure the level translator correctly: Ensure that the level translator is configured correctly, with the pull-down resistor disabled and the input impedance compatible with the output impedance of the Orin NX device.
- Add a pull-up resistor: Add a pull-up resistor to the reset signal to ensure that it’s pulled high when not connected to the level translator.
- Check the signal integrity: Check the signal integrity of the reset signal and ensure that it’s within the recommended limits.
In comparison to the original carrier board design, your custom carrier board design is introducing a voltage level translator to convert the 18V signal to a 3.3V signal. This is likely the root cause of the issue, as the level translator is not functioning as expected. By addressing the issues mentioned above, you should be able to resolve the problem and ensure that the Orin NX device boots successfully.
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Can you please suggest the Level translator which can be used..??
I suspect the problem in your setup may be the TXB0302DQMR getting confused about the directionality of the signal, since it has auto direction sensing. Are you driving the signal low and then high on the 3.3V (MCU?) side?
Instead of a level shifter you could use an NMOS to GND since there is a 10k pull up on the SYS_RESET on the module side. Drive a high to the NMOS gate when you want to assert SYS_RESET low and then drive low to the NMOS to let the signal float and the module will de-assert when ready.
Hey chris,
If i use NMOS, the operation becomes inverted. As per my requirement, i’ll get an active low signal i.e. Master reset from external, The Orin Nx should reset when Master reset will go low and SYS_reset should be floating and should be available for Orin nx for peripheral reset when master reset is high.
Can i use this level shifter TXS0101 FOR SYS RESET.
-Venkat.
While the TXS0101 is compatible with open drain, the bidirectionality could be problematic. The SYS_RESET is bidrectional so the module side’s power sequencer will drive low as needed to meet the SoC’s power sequence requirement. That could cause the TXS0101 to drive low against what is driving it (MCU?).
This makes the NMOS ideal for SYS_RESET since it can only drive low and will not feed back to the side controlling the gate. Since your case is inverted, you could add an inverter+NMOS.
Another option is a SN74LVC1G07 single buffer with open drain output. It will drive low when your controller drives low but it will open (not drive high) when the controller side drives high, still allowing the open drain SYS_RESET to function correctly.
Hi Chris,
Thanks for the clarification. Will implement with SN74LVC1G07.
In addition to this, I have used sys reset for implementing power sequencing of interface voltage rails such as VCC_3V3. I have fed sys reset to SN74LV1T125 for getting 3.3V level sys reset for enabling my voltage regulators. Even here i’m facing the same issue, when i’m connecting to SN74LV1T125, The sys reset will be permanently pulled low. When disconnected, The sys reset behavior will be fine. Can you comment on this.
Regards,
Venkat.
Can you provide a diagram showing the connections to SN74LV1T125 and the source of the 3.3V VCC to the SN74LV1T125?
Hi Chris,
Please find the images attached.
The sysreset from orin nx is fed to SN74LV1T125 and the output of buffer is fed to the enable pin of voltage regulator.
-Venkat.
It looks like you are powering U23 from the same VCC_3V3 rail that you are trying to enable on U3 with the BUCK_3V3_EN1 output of U23.
Side question - is “BUCK_3V3_EN1” on U23 a typo in the net name and it is intended to match the “BUCK_3V3_EN” signal on R15 for U3? The rest of my answer assumes this should be the same net.
U23 won’t function properly without VCC_3V3 enabled but VCC_3V3 won’t enable without U23 outputting BUCK_3V3_EN properly. It is a chicken-egg situation. SYS_RESET going high on the input to U23 will partially backfeed power into it and may cause unknown/unexpected output on the BUCK_3V3_EN signal. U23 should be powered by a rail in the system that is already powered on before this stage, perhaps the “VREG_1” rail to which the U3’s PGOOD pulls up, if it is a valid input voltage for U23.
Hi Chris,
Sorry for the typo error, The voltage rail powering the U23 is a different 3V3 not the VCC_3V3 generated and the net name BUCK_3V3_EN1 is also a typo error.
Hi Chris,
Any clue on this issue..??
-Venkat.
At a high level: disconnect or remove any other components that may be connected to the reset signal to narrow down what part of the circuit is making it stay low. You could try scoping the reset and signals related to those other connected devices and their power rails to see if anything sequences incorrectly or is in an unexpected state/level.
It’s difficult to give more detailed recommendations if the provided schematics have multiple typos in the net names.
