Hi,
I’m currently trying to get SPI1 and SPI3 working on our custom board. I’m using spidev_test as the first way of testing if loopback works (by shorting MISO and MOSI) - while doing this I am also monitoring the clock and chip-select pins.
Here is the result of SPI1 (If my analysis is correct, this is spi@3210000 in the device tree and enumerates as spidev0.* in Linux)
(I don’t have an image, but I can see that CS0 is HIGH on idle and transitions LOW during the write - this is what I expected)
Here is the result of SPI3 (spi@3230000) in the device tree and enumerates as spidev2.* in Linux)
(I can see that CS0 is HIGH on idle and transitions LOW during the write, also that MOSI has data coming out. However, there is still nothing on the RX using spidev tool)
Here is my device tree entry;
spi@3210000{ /* SPI1(SPI0) - TX to MCU*/
status = "okay";
spi@0 { /* chip select 0 */
compatible = "tegra-spidev";
reg = <0x0>;
spi-max-frequency = <50000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
/* spi@1 chip select 1 removed */
};
spi@3230000{ /* SPI3(SPI1) - RX from MCU */
status = "okay";
spi@0 { /* chip select 0 */
compatible = "tegra-spidev";
reg = <0x0>;
spi-max-frequency = <50000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
/* spi@1 chip select 1 removed */
};
Here is my pinmux; (based on generating from spreadsheet)
spi1_sck_pz3 {
nvidia,pins = "spi1_sck_pz3";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
spi1_miso_pz4 {
nvidia,pins = "spi1_miso_pz4";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
spi1_mosi_pz5 {
nvidia,pins = "spi1_mosi_pz5";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
spi1_cs0_pz6 {
nvidia,pins = "spi1_cs0_pz6";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
spi1_cs1_pz7 {
nvidia,pins = "spi1_cs1_pz7";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
........
spi3_sck_py0 {
nvidia,pins = "spi3_sck_py0";
nvidia,function = "spi3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
spi3_miso_py1 {
nvidia,pins = "spi3_miso_py1";
nvidia,function = "spi3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
spi3_mosi_py2 {
nvidia,pins = "spi3_mosi_py2";
nvidia,function = "spi3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
spi3_cs0_py3 {
nvidia,pins = "spi3_cs0_py3";
nvidia,function = "spi3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
spi3_cs1_py4 {
nvidia,pins = "spi3_cs1_py4";
nvidia,function = "spi3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
I would note that the signals are also connected to a level translator, as per this image;
I have tried several things such as using cs-gpios instead of hw based. This results in spidev TX/RX working successfully for both SPI1 and SPI3, but I can see that the chip select pin is not driven low at all during a write. The changes I made for cs-gpios are as follows; (add cs-gpios, num-cs and remove nvidia,enable-hw-based-cs).
spi@3230000{ /* SPI3(SPI1) - RX from MCU */
status = "okay";
num-cs = <1>;
cs-gpios = <&tegra_main_gpio TEGRA234_MAIN_GPIO(Y, 3) GPIO_ACTIVE_LOW>;
spi@0 { /* chip select 0 */
compatible = "tegra-spidev";
reg = <0x0>;
spi-max-frequency = <50000000>;
controller-data {
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
/* spi@1 chip select 1 removed */
};
I also modified the pinmux (re-generated spreadsheet) - essentially just set from nvidia,function = “spi3”; to nvidia,function = “rsvd1”; and I can see this in the gpio kernel debug;
root [ ~ ]$ cat /sys/kernel/debug/gpio | grep -i spi
gpio-473 (PY.03 |spi2 CS0 ) out hi ACTIVE LOW
Does anyone have any idea on what the problem might be?
Thank you in advance.