or cam0, I can use lane_polarity according to the manual description to solve the problem of P/N confusion. I only need to add a line of configuration to the device tree.
I also set lane_polarity to 6, but it doesn’t seem to take effect. Could this parameter theoretically be used in the V4L2 framework? If it doesn’t work, are there any other solutions?
did you meant you’re able to fetch the stream via nvarguscamerasrc, but it failed with v4l2 IOCTL?
please check you’re accessing to the same node, since it’s not always /dev/video0 maps to sensor-id=0.
For some cameras (imx519) I used the isp framework. I can use the camera directly by modifying the device tree lane_polarity parameter.Both cam0 and cam1 work fine
What I am adapting now is another camera. For some reasons, I do not use an isp. Setting lane_polarity in the device tree does not allow me to use the cam0 interface. I can’t get the data using v4l2-ctl.Neither v4l2 nor gstreamer can get the data.
I understand what you mean.
But my device tree and configuration can run on Jetson Nano and Jetson Xavier Nx. Is there anything else we should pay attention to in the orin series?
What I explained before may be a bit redundant, but what you said here is correct. For example, when I am on imx519, I can receive data using nvarguscamerasrc, but v4l2 IOCTL cannot.
as mentioned, it’s not always /dev/video0 maps to sensor-id=0.
you may also check the position property in the tegra-camera-platform fields.
taking dual camera as an example, it’s sensor-id=0 to enable camera with position="rear",
whereas it’s sensor-id=1 to enable camera with position="front"
hence,
please double check you’re accessing to the same node.
I’ve tried modifying the position and making sure they correspond, but the state doesn’t change. Everything is fine in the status of cam1, but cam0 does not work.
root@ubuntu:/home/jetson# /opt/nvidia/camera/nvcapture-status-decoder 190.107234: rtcpu_nvcsi_intr: tstamp:6952138263 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x04000004
NVIDIA camera capture status decoder utility (Version 2.00)
Copyright (C) 2019-2020, NVIDIA Corporation. All rights reserved.
Class: Global
Type: PHY_Interrupt0
PHY: 0
CIL: 1
Stream: 0
VC: 0
Status: 67108868
Timestamp: 6952138263
PHY_Interrupt0 : 0x0000000004000004
-cil_data_lane_sot_mb_err0 [ 2]: 1
More than one bit error detected on the data lane [A/B]0 sync word
-dphy_cil_deskew_calib_err_lane1 [26]: 1
DPHY deskew calibration not complete on data lane [A/B]1. Happen when the calibration sequence length is not long enough
is it one-lane on CSI-B to report the issue? please try to configure lane_polarity = "4"; //0100 for testing.
besides, are you using Orin NX/Nano developer kits, or, it’s Orin SOM on Xavier NX carrier board?
