Hi Vidyas,
I’m addressing directly to you because I’ve seen a similar error discussion at https://devtalk.nvidia.com/default/topic/963078/?comment=4976394
where you gave an advice…
We had a family of the device drivers for the FPGA modules behind the pcie-axi bridge.
On the 23.2 it was Ok.
On 24.2 SMMU becomes active and denys an access of our VDMA to a buffer.
After start of VDMA data transfer we can see the errors shown below.
We cannot see a real data in the buffer. It seems SMMU prevents to put data via PCIe bridge to chosen memory block.
[ 186.529950] smmu_dump_pagetable(): fault_address=0x00000000c0000000 pa=0xffffffffffffffff bytes=ffffffffffffffff #pte=0 in L2
[ 186.541416] mc-err: (0) csw_afiw: EMEM decode error on PDE or PTE entry
[ 186.548315] mc-err: status = 0x60010031; addr = 0xc0000000
[ 186.554102] mc-err: secure: no, access-type: write, SMMU fault: nr-nw-s
[ 186.560975] smmu_dump_pagetable(): fault_address=0x00000000c0c7a800 pa=0xffffffffffffffff bytes=ffffffffffffffff #pte=0 in L2
[ 186.572330] mc-err: (0) csw_afiw: EMEM decode error on PDE or PTE entry
[ 186.579101] mc-err: status = 0x60010031; addr = 0xc0c7a800
[ 186.584789] mc-err: secure: no, access-type: write, SMMU fault: nr-nw-s
[ 186.592565] smmu_dump_pagetable(): fault_address=0x00000000c17f7000 pa=0xffffffffffffffff bytes=ffffffffffffffff #pte=0 in L2
[ 186.603956] mc-err: (0) csw_afiw: EMEM decode error on PDE or PTE entry
[ 186.610649] mc-err: status = 0x60010031; addr = 0xc17f7000
[ 186.616347] mc-err: secure: no, access-type: write, SMMU fault: nr-nw-s
[ 186.623194] smmu_dump_pagetable(): fault_address=0x00000000c2432700 pa=0xffffffffffffffff bytes=ffffffffffffffff #pte=0 in L2
[ 186.634509] mc-err: (0) csw_afiw: EMEM decode error on PDE or PTE entry
[ 186.641234] mc-err: status = 0x60054031; addr = 0xc2432700
[ 186.646960] mc-err: secure: no, access-type: write, SMMU fault: nr-nw-s
[ 186.655577] mc-err: Too many MC errors; throttling prints
Memory is reserved in DT:
reserved-memory {
ranges;
vdmabuffer@C0000000 {
reg = <0x0 0xc0000000 0x0 0x10000000>;
};
};
pcie-controller {
pci@1,0 {
ranges= <0xc2000000 0x0 0x20000000 0xc2000000 0x0 0x20000000 0x0 0x20000000>;
pci@3,0 {
reg = <0x10000 0x0 0x0 0x0 0x0>;
compatible = "artcg,ag-parent-alpha";
ranges = <0x0 0xc2000000 0x0 0x20000000 0x100000>;
axi_vdma_0@00000000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "artcg,ag-vdma-alpha";
reg = <0x00000 0x1000 0x20000 0x1000>;
reg_names = "addr", "numreg_addr";
ranges;
artcg,memory-pool = <0xc0000000>;
artcg,num-frames = <0x8>;
artcg,bpp = <0x2> ;
Please advise.
Thank you,
Alex