Hello.
I have a AGX Xavier and I’d like to test pcie loopback mode.
And I could read a link below.
But this is just shorting tx and rx lines.
Is it possible to test it by setting related registers internally with gen3 or gen4?
And If it’s possible, can you share me related documents or something like that?
Thank you.
loopback can be verified by shorting Tx and Rx lanes externally.
Please make sure to set the max-speed in the respective DT controller’s node to ‘2’ (as Gen-3 & 4 need equalization and would fail in loop back configuration).
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