PCIe switch Downstream port detection issue

Hello all,

I am currently working on nvidia jetson xavier nx based custom device. We had attached microchip based PCIe switch with custom board, and 5 down stream ports are attached with PCIe switch. PCIe switch is detected on pcie@141e0000 address. I have doubt in device tree file. Can you please help me to resolve this doubt on asap.

  1. When we are attaching PCIe switch on PCIe slot then do we need to write register ranges in device tree file? PCIe switch is based on Gen-4 x4 configuration.
  2. Is it possible to provide sample device tree file for PCIe switch Up stream port and downstream port configuration? or if possible, provide us document to verify PCIe configurations in device tree file.
  3. Some times kernel was crashing when it is tring to load pci driver. It will print memory allocation logs at the time of crashing.

Please reply me asap for resolve all this doubts. Thank you in advance.

Thanks and regards


Is there any update on this? Currently we are stuck here with this issue. Please help us to resolve this issue quickly.

Thanks and regards

1 Like

Sorry for the late response, is this still an issue to support? Thanks


Yes, still we are facing the same issue. Please help us to resolve it.

Thanks and regards


In Xavier there is no controller with 141e0000 address.
There is no need for any device update to detect switch, default root port controller node in platform dts file is enough to enumerate all ports.

You can refer to file for example DT node.


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