Problem with 4 lane mipi from FPGA

Hi!

We’re getting data from an FPGA to the Xavier NX via mipi.
2 lanes works great.
But trying to move to 4 lanes we get errors and crashes from the nvcsi cpu.

What have we done wrong?

We’ve tried to boost the clocks and add serdes_pix_clk to the devtree. But no changes at all.

I’ll add the trace below.
Any help would be greatly appreciated.

# tracer: nop
#
# entries-in-buffer/entries-written: 123317/123317   #P:6
#
#                                _-----=> irqs-off
#                               / _----=> need-resched
#                              | / _---=> hardirq/softirq
#                              || / _--=> preempt-depth
#                              ||| /     delay
#           TASK-PID     CPU#  ||||   TIMESTAMP  FUNCTION
#              | |         |   ||||      |         |
     kworker/0:2-4799    [000] .... 59393.889633: rtcpu_string: tstamp:1856698814935 id:0x04010000 str:"VM0 deactivating."
     kworker/0:2-4799    [000] .... 59402.849652: rtcpu_string: tstamp:1856978228464 id:0x04010000 str:"VM0 activating."
     kworker/0:2-4799    [000] .... 59402.905630: rtcpu_vinotify_event: tstamp:1856979384795 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:59423324515072 data:0xcd9ce50010000000
     kworker/0:2-4799    [000] .... 59402.905634: rtcpu_vinotify_event: tstamp:1856979384961 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:59423324527168 data:0x0000000031000001
     kworker/0:2-4799    [000] .... 59402.905635: rtcpu_vinotify_event: tstamp:1856979385127 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:59423324583488 data:0xcd9ce20010000000
     kworker/0:2-4799    [000] .... 59402.905636: rtcpu_vinotify_event: tstamp:1856979385269 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:59423324595712 data:0x0000000031000002
     kworker/0:2-4799    [000] .... 59402.961621: rtcpu_nvcsi_intr: tstamp:1856980884155 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000110
     kworker/0:2-4799    [000] .... 59402.961624: rtcpu_nvcsi_intr: tstamp:1856980884614 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000088
     kworker/0:2-4799    [000] .... 59402.961626: rtcpu_nvcsi_intr: tstamp:1856980884986 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000088
     kworker/0:2-4799    [000] .... 59402.961627: rtcpu_nvcsi_intr: tstamp:1856980886645 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
     kworker/0:2-4799    [000] .... 59402.961628: rtcpu_nvcsi_intr: tstamp:1856980887546 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
     kworker/0:2-4799    [000] .... 59402.961629: rtcpu_nvcsi_intr: tstamp:1856980887999 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
     kworker/0:2-4799    [000] .... 59402.961630: rtcpu_nvcsi_intr: tstamp:1856980889354 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
     kworker/0:2-4799    [000] .... 59402.961631: rtcpu_nvcsi_intr: tstamp:1856980889805 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
     kworker/0:2-4799    [000] .... 59402.961632: rtcpu_nvcsi_intr: tstamp:1856980890256 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
     kworker/0:2-4799    [000] .... 59402.961633: rtcpu_nvcsi_intr: tstamp:1856980891160 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000088
     kworker/0:2-4799    [000] .... 59402.961634: rtcpu_nvcsi_intr: tstamp:1856980891613 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000088
...
1 Like

There have data lane control error(err_intr_cil_data_lane_ctrl_err0_a)
Did you probe 4 data lanes to confirm the output configure as 4 lanes?

Yes, we’ve been probing all lanes and we can see what looks like good data on all four…

Is this still an issue to support? Any result can be shared? Thanks