Description
A clear and concise description of the bug or issue.
Environment
GPU Type:Jetson Xavier NX emmc version
Nvidia Driver Version:
Operating System + Version:JetPack_5.1.5_Linux_JETSON_XAVIER_NX_TARGETS
Python Version (if applicable):
TensorFlow Version (if applicable):
PyTorch Version (if applicable):
Baremetal or Container (if container which image + tag):
Relevant Files
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Steps To Reproduce
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Dear NVIDIA Support Team,
I am currently working on a custom hardware platform where NVIDIA Jetson Xavier NX is configured as a PCIe Root Complex and a Xilinx Zynq UltraScale+ MPSoC (XCZU15EG) is configured as a PCIe Endpoint using the PS PCIe controller (Bank 505).
PCIe link training and enumeration are completed successfully, and the device is detected correctly on the Jetson Xavier NX using lspci. BAR0 is enabled on the Zynq endpoint and is mapped to valid AXI-accessible memory (BRAM/DDR). The BAR size and type are correctly reported on the Jetson side.
The issue I am facing is related to PCIe data transfer in the Endpoint-to-Root direction:
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When the Jetson Xavier NX writes data to the Zynq BAR0 region, the Zynq is able to read the data correctly.
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However, when the Zynq writes data into its BAR-mapped memory, the Jetson Xavier NX is unable to read the updated value from the BAR region.
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Zynq software uses Xil_Out32() to write data, and cache handling is being reviewed/disabled during testing.
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Jetson accesses the BAR region via /dev/mem using mmap and performs 32-bit read operations.
My understanding is that BAR memory access is Root-initiated, and I would like clarification on the following points from NVIDIA’s side:
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Are there any Jetson Xavier NX–specific requirements, cache settings, or memory barriers needed to ensure correct BAR read visibility when data is written by the PCIe Endpoint?
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Does Jetson require any additional configuration to properly read updated BAR memory contents written by the Endpoint?
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Is BAR memory on Jetson treated as non-coherent, and are there recommended practices to ensure correct data synchronization?
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Are there any known limitations or errata related to PCIe BAR memory reads on Jetson Xavier NX when used with third-party PCIe endpoints?
This information will help us determine whether the issue is related to PCIe protocol behavior, cache coherency, or Jetson-side configuration.
Thank you for your support. I look forward to your guidance.
ps_pcie_design.pdf (163.1 KB)
