Register 0x70000820 is undocumented and used here on tegra124-soc.dtsi

pinmux: pinmux {
compatible = “nvidia,tegra124-pinmux”;
reg = <0x0 0x70000868 0x0 0x164 /* Pad control registers /
0x0 0x70003000 0x0 0x434 /
Mux registers /
0x0 0x70000820 0x0 0x8>; /
MIPI pad control */

at page 912. APB_MISC_GP_MIPI_PAD_CTRL_0

there is only bit 1 described, where as you can see, here bit 3 is set.

So why arent the rest of the bit described , and what it does as 0x8?