/* Dynamic pinmux config for DMIC3 */ has no regular gpio state.

What controls the dynamic pin mux anyhow? How can I change it to gpio?

I’m trying to get module pin E16 to be GPIO3_PAA01.
I used the excel spreadsheet to generate the gpio.dtsi file to see the syntax.
It seems that I can’t get control of the pin, and it reverts to dmic function.
I don’t see any fragments in the dmesg for this.

DTS that I added to the top level:

pinmux@2430000 {
	                can_gpio1_paa1 {
				nvidia,pins = "can_gpio1_paa1";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

quill-common.dtsi

pinmux@2430000 {

...

                /* Dynamic pinmux config for DMIC3 */
                dmic3_dap_active_state: dmic3_dap_active {
                        dmic_can_gpio0_paa0 {
                                nvidia,pins = "can_gpio0_paa0";
                                nvidia,function = "dmic3";
                        };
                        dmic_can_gpio1_paa1 {
                                nvidia,pins = "can_gpio1_paa1";
                                nvidia,function = "dmic3";
                        };
                };
                dmic3_dap_inactive_state: dmic3_dap_inactive {
                        dmic_can_gpio0_paa0 {
                                nvidia,pins = "can_gpio0_paa0";
                                nvidia,function = "dmic5";
                        };
                        dmic_can_gpio1_paa1 {
                                nvidia,pins = "can_gpio1_paa1";
                                nvidia,function = "dmic5";
                        };
                };

Resulting dts from proc:

dmic3_dap_active {
			phandle = <0xeb>;
			linux,phandle = <0xeb>;

			dmic_can_gpio0_paa0 {
				nvidia,function = "dmic3";
				nvidia,pins = "can_gpio0_paa0";
			};

			dmic_can_gpio1_paa1 {
				nvidia,function = "dmic3";
				nvidia,pins = "can_gpio1_paa1";
			};
		};

...

		dmic3_dap_inactive {
			phandle = <0xec>;
			linux,phandle = <0xec>;

			dmic_can_gpio0_paa0 {
				nvidia,function = "dmic5";
				nvidia,pins = "can_gpio0_paa0";
			};

			dmic_can_gpio1_paa1 {
				nvidia,function = "dmic5";
				nvidia,pins = "can_gpio1_paa1";
			};
		};

...

		can_gpio1_paa1 {
			nvidia,enable-input = <0x1>;
			nvidia,tristate = <0x1>;
			nvidia,function = "rsvd0";
			nvidia,pins = "can_gpio1_paa1";
			nvidia,pull = <0x1>;
		};

The excel spreadsheet only deals with the pinmux. For example, configure one pin as SFIO or GPIO.
It is not for kernel but for bootloader.

You could use sysfs after boot up to control if it is a GPIO.
https://devtalk.nvidia.com/default/topic/1020887/jetson-tx2/how-to-configure-a-gpio-on-tx2-/

To be clear here, My board has a bunch of gpio.They all have the proper voltage translators in banks of 4. This pin is an input and always reads a 1 no matter the input voltage. All of the others are working fine. They all use the /sys/class/gpio interface.

Thanks!!

Thanks for clarification.

Could you compare the pinmux setting between the working GPIOs with the non-working one?

The fast way is to compare the state of cfg file (tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg).

tegra186-mb1-bct-pinmux-quill-p3489
-1000-a00.cfg

I don’t have any of these files on the host

Pinmux version 1.0

Input pinmux file name: tegra18x-p3489-1000-a03-icvm-pinmux.dtsi

Input gpio file name: tegra18x-p3489-1000-a03-icvm-gpio-default.dtsi

Generation date: 2017-12-01 10:44

PLEASE DO NOT EDIT THIS FILE

This is autogenerated file using the script pinmux-dts2cfg.py

– line 50 is working gpio input gpio298
pinmux.0x0c2f1c40 = 0x00000001; # CONFIG AA2
pinmux.0x0c303038 = 0x00000000; # GPIO can_gpio2_paa2

– line 303 still not usable as gpio297
pinmux.0x0c303030 = 0x00000402; # can_gpio1_paa1: dmic5, tristate-disable, input-disable

Tried this, didn’t work …

dmic@2904000 {
                status = "disabled";
        };
        dmic@2904100 {
                status = "disabled";
        };
        dmic@2904200 {
                status = "disabled";
        };
        dmic@2904300 {
                status = "disabled";
        };


        gpio@c2f0000 {
                my_aon_gpio1_name {
                        gpio-hog;
                        status = "okay";
                        output-low;
                        gpios = <TEGRA_AON_GPIO(AA, 1) 0>;
                        label = "my_aon_gpio1";
                };
        };


        pinmux@2430000 {
                can_gpio1_paa1 {
                        nvidia,pins = "can_gpio1_paa1";
                        nvidia,function = "rsvd0";
                        nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                        nvidia,tristate = <TEGRA_PIN_ENABLE>;
                        nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                };
        };

Not sure what that extra 0 is for on the gpios line but this seems to work

gpio@c2f0000 {
                my_aon_gpio1_name {
                        gpio-hog;
                        status = "okay";
                        input;
                        gpios = <TEGRA_AON_GPIO(AA, 1) 0>;
                        label = "my_aon_gpio1";
                };
        };

dmesg

[    0.266071] GPIO line 296 (my_aon_gpio01) hogged as input

Finally got the dmic 3 to shut off, but all that does is change to dmic 5, which doesn’t exist as far as I can tell.

dmic@2904200 {
                        reg = <0x2904200 0x100 0xc303000 0x1f0>;
                        nvidia,ahub-dmic-id = <0x2>;
                        pinctrl-0 = <0xeb>;
                        pinctrl-1 = <0xec>;
                        compatible = "nvidia,tegra210-dmic";
                        clock-names = "dmic3", "pll_a_out0", "sync_dmic3";
                        clocks = <0xd 0x96 0xd 0xf6 0xd 0x101>;
                        nvidia,is-pinctrl = <0x1>;
                        status = "disabled";
                        phandle = <0xdd>;
                        pinctrl-names = "dap_active", "dap_inactive";
                        linux,phandle = <0xdd>;

                        prod-settings {
                                #prod-cells = <0x4>;

                                prod {
                                        prod = <0x1 0x28 0xffff 0x6441 0x1 0x30 0xffff 0x6441>;
                                };
                        };
                };

Right after boot up the PADCTL_AO_HV_CFG2TMC_CAN_GPIO0_0 register looks like this

ubuntu@tegra-ubuntu:~/test$ sudo ./devmem2 0x0c303030 w
Value at address 0xC303030 (0x7fb19bd030): 0x6052

The 2 is DMIC5, no pull up or down
The 5 is
GPIO_SF_SEL = 0 = GPIO
E_PBIAS_BUF = 1 = ENABLE
E_INPUT = 0 = DISABLE
TRISTATE = 1 = ENABLE

If I write E_INPUT to a 1, it always reads back 0.
I don’t think that the SF matters at this point since GPIO is selected and it is hogged.

Right now I have gpio393 (as output) connected to gpio398 and gpio298 (as input). This all works like I think it should.

Also, gpio394 (as output) is connected to gpio297 and gpio389 (as input).

In this case, gpio297 always reads 0, even when gpio394 is 1.

ubuntu@tegra-ubuntu:~/test$ ./lbgpio.sh
---- L 0 H 1 -----
0
0
0
1
---- L 1 H 0 -----
1
1
0
0

When I change the PULL_DOWN value, I get the bit stuck the other way

ubuntu@tegra-ubuntu:~/test$ sudo ./devmem2 0x0c303030 w 06040
Value at address 0xC303030 (0x7f95b45030): 0x6052
Written 0xC20; readback 0x400
ubuntu@tegra-ubuntu:~/test$ ./lbgpio.sh
---- L 0 H 1 -----
0
0
1
1
---- L 1 H 0 -----
1
1
1
0

To summarize, I can’t change the value of E_INPUT, and I can’t read the voltage on the pin.
I’m not sure what else there is to change.

Help!!

Hi,

p3489 is for TX2i and p3310 is for TX2. Is this GPIO the only one in your design with direction as input? If not, are other input gpios working fine?

Yep,
It says in the last message "

Right now I have gpio393 (as output) connected to gpio398 and gpio298 (as input). This all works like I think it should.

Also, gpio394 (as output) is connected to gpio297 and gpio389 (as input).
"

So yes
output gpio393 <-- OK
output gpio394 <-- OK
input gpio398 <-- OK
input gpio298 <-- OK
input gpio297 <-- BAD
input gpio389 <-- OK

I am using a TX2i

gpios = <TEGRA_AON_GPIO(AA, 1) 0>;

[ 0.265968] GPIO line 297 (my_aon_gpio10) hogged as input

gpios = <TEGRA_AON_GPIO(AA, 0) 0>;

[ 0.266031] GPIO line 296 (my_aon_gpio00) hogged as input

Could you compare the pinmux setting between AA1 and AA0? Is there any difference?

PAA.0 same register map as 1. This isn’t present on my board

ubuntu@tegra-ubuntu:~/test$ sudo ./devmem2 0x0c303028 w
Value at address 0xC303028 (0x7f93612028): 0x6052

PAA.1 <-- This is the bit that will not function as an input

ubuntu@tegra-ubuntu:~/test$ sudo ./devmem2 0x0c303030 w
Value at address 0xC303030 (0x7fa5e9c030): 0x6052

PAA.2 <-- This bit works fine. The register map is different from the rest.

ubuntu@tegra-ubuntu:~/test$ sudo ./devmem2 0x0c303038 w
Value at address 0xC303038 (0x7f91a6c038): 0x59

Either PAA.1 is incapable of operating as an input, or there is insufficient/incorrect documentation.

According to the TRM, there can be no input value passed without E_INPUT=1. None of these registers will read back 0x20 when that value is written.
The bit is either not present or is not r/w.

This I/O does not function as advertised.

BConklin,

Do you ever change your pinmux file “tegra186-mb1-bct-pinmux-quill-p3489-1000-a00.cfg” from pinmux spreadsheet?

They are 0x434

You see,

Section 8.3 MPIO Pad and Brick Description has Figure 27 that shows the Pad Diagram with Pinmuxing Structure.

We never did find out how or what comes along and sets the PM bits to 1 or 2. It doesn’t appear that there is any way to stop that.
I even modified the kernel source for the pinmux driver so that it didn’t have that option.

That was all wasted time because the GPIO_SF_SEL routes everything around the pinmux anyhow.
I found the gpio-hog section from someone else that was having similar issues.

That was all wasted time because the input path is cut off completely when the E_INPUT bit is low, and it cannot be set high.

So something is severley wrong with the documentation, and it doesn’t appear that anyone knows enough about this to get an answer.

Hi BConklin,

Sorry that I got lost about your comment. What are “they” and why 0x434? Could you elaborate about it?

Also, if I remembered correctly, there is no use to modify gpio state in kernel dtsi when pinmux does not set the pin as GPIO. What you added in comment#1 #6 and #7 seens are all in kernel dts. It will not change the pinmux setting.

So my question is same as my previous comment: did you every change the pinmux setting by using the pinmux spread sheet? I notice your comment

“I used the excel spreadsheet to generate the gpio.dtsi file to see the syntax.
It seems that I can’t get control of the pin, and it reverts to dmic function.”

Does it mean the spreadsheet have error?

If so, could you share the content in your pinmux file (tegra186-mb1-bct-pinmux-quill-p3489-1000-a00.cfg)? Didn’t it get updated after you use pinmux spreadsheet to create a new one?

Could please you compare the working pin state with the unfunctional one in the config?

#For example, you said paa2 is working and from the register, the value is 
# PAA.2 <-- <b>This bit works fine.</b> The register map is different from the rest.
ubuntu@tegra-ubuntu:~/test$ sudo ./devmem2 0x0c303038 w
Value at address 0xC303038 (0x7f91a6c038): /

#While  PAA1 is not working.

# PAA.1 <-- <b>This is the bit that will not function as an input</b>
ubuntu@tegra-ubuntu:~/test$ sudo ./devmem2 0x0c303030 w
Value at address 0xC303030 (0x7fa5e9c030): 0x6052

These two are already in different states in the pinmux config. PAA2 is configured as RSVD pin and PAA1 is dmic5.

As below debugfs tells us, PAA1 and PAA2 are different.

root@nvidia-desktop:/sys/kernel/debug/pinctrl/2430000.pinmux# cat pinmux-pins |grep PAA
pin 208 (CAN_GPIO0_PAA0): tegra210-dmic.2 (GPIO UNCLAIMED) function dmic5 group can_gpio0_paa0
[b]pin 209 (CAN_GPIO1_PAA1): tegra210-dmic.2 (GPIO UNCLAIMED) function dmic5 group can_gpio1_paa1
pin 210 (CAN_GPIO2_PAA2): (MUX UNCLAIMED) (GPIO UNCLAIMED)[/b]
pin 211 (CAN_GPIO3_PAA3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 212 (CAN_GPIO4_PAA4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 213 (CAN_GPIO5_PAA5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 214 (CAN_GPIO6_PAA6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 215 (CAN_GPIO7_PAA7): (MUX UNCLAIMED) (GPIO UNCLAIMED)