Hello,
Question about AGX Orin Hardware implementation.
- I design 1Gbethernet using RGMII interface.
i have a qustions about RGMII lines. extended externally. do you populate termination resistors near the MAC Tx (ORIN) side as well ?
I can’t find this information on the Table 8.2
https://developer.download.nvidia.com/assets/embedded/secure/jetson/agx_orin/Jetson_AGX_Orin_Series_Design_Guide_DG-10653-001_v1.2.pdf?xWZAA6BKknwzeYLf4b80O1m4BC6k0KUbapDG2zfmK6cmY0U7aQLTeDyU4Oa8mPQMccqsbc6_K5TztMSTzksUtQADn_QBgzvTutZG89EUTSfNoLh5c6XAYQvzGCEkOBSuMrWqeBSkqGignPywfHyMKHikA3VfE4_Lf5HxUt9rxiuf1Ct6uwulc1veybRPc3y2-n7OtIpefEQepAJ-V1Dl&t=eyJscyI6IndlYnNpdGUiLCJsc2QiOiJkZXZlbG9wZXIubnZpZGlhLmNvbS9lbWJlZGRlZC9kb3dubG9hZHMjP3NlYXJjaD1PUklOIn0=