Setting SCLK and FS I2S interface, device tree configuration

Robotics & Edge Computing Jetson & Embedded Systems Jetson Orin Nano
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1

So I’m trying to interface a CS4272 with the Jetson Orin Nano and i had a few questions about the I2S interface on the Orin Nano. I’m under the impression that configuring the I2S bus via jetson-io configures the I2S interface at a high level. So the clocks for SCLK and FS are not set, i was wondering how to set these, whether through scripts or device tree configuration, i am new to the latter. Here is what i have for the device tree configuration:

So i would either modified the auto generated overlay or create a new one (cs4272.dts) with the explicit clock settings, here is the device tree configuration I’ve been looking at, do keep in mind that i have not created or applied a new .dts, this is more so a check before i do all of that :

/dts-v1/;
/plugin/;

/ {
    fragment@0 {
        target-path = "/";
        __overlay__ {
            cs4272: cs4272 {
                compatible = "cirrus,cs4272";
                status = "okay";
            };
        };
    };

    fragment@1 {
        target = <&i2s1>; // Target the Jetson's I2S controller
        __overlay__ {
            status = "okay";
            #sound-dai-cells = <0>;
            // Configure clocks for 48 kHz LRCK, 24-bit depth
            clocks = <&tegra_asrc 1>; // Use ASRC for clock generation
            clock-names = "asrc";
            assigned-clocks = <&tegra_asrc 1>;
            assigned-clock-rates = <12288000>; // MCLK for internal PLL (not used by CS4272)
            // Define I2S format (I²S, 24-bit)
            dai-format = "i2s";
            bitclock-master = <&i2s1>;
            frame-master = <&i2s1>;
        };
    };
};

The i would compile and apply the overlay (not exactly sure if this is the correct way:

dtc -O dtb -o cs4272.dtbo -@ cs4272.dts
sudo cp cs4272.dtbo /boot/
sudo reboot
3

Just to be clear, the MCLK is being generated by an external crystal that will be connected to the XTI and XTO pins on the CXS4272 CODEC to generate a 12.288 MHZ clock signal. So the LRCK and SCLK need to be 48 kHz (the sampling rate) and 3.072 MHz respectively.

5

Hi,

Greetings!

Please note that jetson-io configures pins as Special function I/O (DIN, DOUT, SCLK, BCLK) instead of GPIO and does not enable clocks

Further, I see issues with the DTS entries. to resolve the same, please refer to the guide to integrate new sound card on 40 pin header at Audio Setup and Development — NVIDIA Jetson Linux Developer Guide 1 documentation

Also, having an dtbo in rootfs shall not result in its application atop kernel dtb. Please add the entries per above guide and in the paths mentioned in section Audio Setup and Development — NVIDIA Jetson Linux Developer Guide 1 documentation so that the modified entries take effect

Also, I see that you want to operate codec as clock supplier, so you may have to setup i2s mode via mixer controls. More info at Audio Setup and Development — NVIDIA Jetson Linux Developer Guide 1 documentation

Feel free to reach for further queries

Thanks

6

I will read into this more as i am fairly new to developing with the jetson orin nano and I will get back to you with any questions i have regarding these topics.

Also i was under the impression that the Orin Nano could not generate a clock signal from one of its GPIOs, hence the use of an external parallel resonant crystal connected to the codec. However, from another topic i was told otherwise as shown here:

I’m assuming this is another device tree configuration I would have to look into or what would be the correct course of action in regards to looking into this configuration.

NOTE: I made a typo, the codec I am using is the CS4272 (NOT CXS4272)

Just to be clear, do I still need to configure the pins via jetson-io and look into device-tree configurations or just the latter?

7

Hi,

Sure

Yes

Yet it can as can be referred from available Board Interfaces at Audio Setup and Development — NVIDIA Jetson Linux Developer Guide 1 documentation

You need to configure aud_mclk via Jetson-IO for it to behave as a clock instead of GPIO

Audio Setup and Development — NVIDIA Jetson Linux Developer Guide 1 documentation refers to use of AUD_MCLK as codec sysclk. This is part of codec integration guide that i pointed earlier

Thanks