Hello, maxe777:
Sorry for that long time delay.
Here are the explanations for the issue you met.
In Orin, GTE only records lower 24 bits (from TSC) in FIFO, and when the timestamp read from GTE FIFO, the actual value is (TSC higher bit) 55:24 + (GTE FIFO counter) 23:0.
Some algorithms are introduced inside GTE for the final timestamp when GTE FIFO is read.
In a simple word, software should read the GTE FIFO within 0.268 second (In Orin, TSC is running at 31.25MHz).
So back to the problem you met.
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When occupancy is set by 1, SPE firmware can always read the GTE FIFO in time. So no error’s observed. If you add more delays inside ISR, you may also get the wrong timestamp.
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The situation may be much worse when occupancy is set more than 1, since for multiple events, the delay is much higher, and when timestamps in GTE FIFO are retrieved, high bits (TSC 55:24) may vary. That’s the error you observed.
In such case, you may still have to
2.1 record every event timestamp (TSC) in ISR, which should guarantee the delay within the value mentioned above.
2.2 when retrieving multiple timestamps in GTE FIFO, correct the timestamps with the value in 2.1, since only the lower 24 bits in GTE FIFO is trustable.
Hope that explains.
br
ChenJian