SPI bus on Jetson NANO L4T 32.4.3 not working

Hi all,
I’m trying to use the SPI1 bus on a Jetson NANO configured using Jetpack 4.4.
I followed the instruction from https://www.jetsonhacks.com/2020/05/04/spi-on-jetson-using-jetson-io/ to enable the SPI1, but it doesn’t work.

I have a SD card with Jetpack 4.3 and the same software works correctly.

Has something changed with L4T 32.4.3?

Could you check the pin status by below command to check if the Z group is enable as GPIO or not after configure by the jetson-io.

cat /sys/kernel/debug/tegra_gpio

Here it is:

$ sudo cat /sys/kernel/debug/tegra_gpio
[sudo] password for myzhar: 
Name:Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL
 A: 0:0 64 40 40 24 00 00 000000
 B: 0:1 00 00 00 00 00 00 000000
 C: 0:2 00 00 00 00 00 00 000000
 D: 0:3 00 00 00 00 00 00 000000
 E: 1:0 00 00 00 00 00 00 000000
 F: 1:1 00 00 00 00 00 00 000000
 G: 1:2 00 00 00 00 00 00 000000
 H: 1:3 fd 99 00 60 00 00 000000
 I: 2:0 07 07 03 02 00 00 000000
 J: 2:1 00 00 00 00 00 00 000000
 K: 2:2 00 00 00 00 00 00 000000
 L: 2:3 00 00 00 00 00 00 000000
 M: 3:0 00 00 00 00 00 00 000000
 N: 3:1 00 00 00 00 00 00 000000
 O: 3:2 00 00 00 00 00 00 000000
 P: 3:3 00 00 00 00 00 00 000000
 Q: 4:0 00 00 00 00 00 00 000000
 R: 4:1 00 00 00 00 00 00 000000
 S: 4:2 80 80 00 00 00 00 000000
 T: 4:3 01 01 00 00 00 00 000000
 U: 5:0 00 00 00 00 00 00 000000
 V: 5:1 02 00 00 02 00 00 000000
 W: 5:2 00 00 00 00 00 00 000000
 X: 5:3 78 08 08 70 00 60 606000
 Y: 6:0 02 00 00 02 00 00 000000
 Z: 6:1 0e 08 08 04 00 06 020600
AA: 6:2 00 00 00 00 00 00 000000
BB: 6:3 00 00 00 00 00 00 000000
CC: 7:0 92 80 80 10 00 12 121200
DD: 7:1 00 00 00 00 00 00 000000
EE: 7:2 00 00 00 00 00 00 000000
FF: 7:3 00 00 00 00 00 00 000000

The pin configure looks fine, did you try the spidev_test for the loopback mode?

1 Like

Just tried:

$ ./spidev_test -v
spi mode: 0x0
bits per word: 8
max speed: 500000 Hz (500 KHz)
TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.
RX | 0F FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 99 BD  | ..............................��

Using: https://github.com/rm-hull/spidev-test

Using loopback:

$ ./spidev_test --loop
can't set spi mode: Invalid argument
Aborted (core dumped)

I performed the same test using the SD Card with JP4.3 and the replies are the same:

$ ./spidev_test -D /dev/spidev0.0
spi mode: 0x0
bits per word: 8
max speed: 500000 Hz (500 KHz)
RX | 0F FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 DE E0  | ..............................��

Hi Myzhar,

After using jetson-io for configuring the pins can you run the following command to see if jetson-io think SPI1 is enabled?

$ sudo /opt/nvidia/jetson-io/config-by-function.py -l enabled
The following functions are enabled on the 40-pin header:
 1. spi1

And the following command to dump the pinmux configuration …

$ sudo grep spi1 /sys/kernel/debug/tegra_pinctrl_reg
Bank: 1 Reg: 0x70003050 Val: 0x0000e044 -> spi1_mosi_pc0
Bank: 1 Reg: 0x70003054 Val: 0x0000e044 -> spi1_miso_pc1
Bank: 1 Reg: 0x70003058 Val: 0x0000e044 -> spi1_sck_pc2
Bank: 1 Reg: 0x7000305c Val: 0x0000e048 -> spi1_cs0_pc3
Bank: 1 Reg: 0x70003060 Val: 0x0000e048 -> spi1_cs1_pc4

And to confirm, by SPI1, you are referring to the SPI pins on 19, 21, 23, 24, 26 of the 40-pin header?

Thanks
Jon

Hi jonathanh,

both the commands work as expected and yes, I’m using the SPI1 on the pins you listed.
Like I wrote above, if I insert an SD card created with JP4.3 everything works, it doesn’t using a JP4.4 SD card.

Is it possible that the size of the buffer of the spidev driver is not correctly set?
I followed this procedure to set it permanently to 20KB. It works with JP4.3, but at this point I have doubts that it is correct for JP4.4.

It is really important to have the correct SPI buffer size, otherwise the thermal image from a FLIR Lepton 3 module cannot be fully received (see my blog post)

Could you try the loopback test with the spidev_test.

Hi Myzhar,

Thanks for the feedback. I don’t see why that would not set the SPIDEV buffer size, but I wanted to ensure that the pinmux is configured as expected first. So to confirm is the output from the following commands the same between JP4.3 and JP4.4?

$ sudo grep spi1 /sys/kernel/debug/tegra_pinctrl_reg
$ sudo grep " C:" /sys/kernel/debug/tegra_gpio

If so then the pinmux should be fine and jetson-io should be working fine. If we can confirm this, then we can focus on the SPI itself. Please note that I typically deal with jetson-io issues and so we can pull in the correct person for SPI once we have eliminated that as the problem.

Thanks
Jon

Good. Here they are:

$ sudo grep spi1 /sys/kernel/debug/tegra_pinctrl_reg
Bank: 1 Reg: 0x70003050 Val: 0x0000e044 -> spi1_mosi_pc0
Bank: 1 Reg: 0x70003054 Val: 0x0000e044 -> spi1_miso_pc1
Bank: 1 Reg: 0x70003058 Val: 0x0000e044 -> spi1_sck_pc2
Bank: 1 Reg: 0x7000305c Val: 0x0000e048 -> spi1_cs0_pc3
Bank: 1 Reg: 0x70003060 Val: 0x0000e048 -> spi1_cs1_pc4

$ sudo grep " C:" /sys/kernel/debug/tegra_gpio
 C: 0:2 00 00 00 00 00 00 000000

Hi myzhar,
spidev driver did not change. It’s same for J4.3 and J4.4
Do you mean that setting bufsize to 20KB works in J4.3 and not in J4.4?
If it is so, it will help catching the problem faster.

Thanks,
Shubhi

Hi myzhar,
Also, can you try to modify Nano kernel dtb with following changes and let me know the results:
spi@7000d400 {
– controller-data {
– nvidia,enable-hw-based-cs;
– nvidia,rx-clk-tap-delay = <7>;
– };
};
Just remove controller-data node from SPI1 (spi@7000d400) in kernel dtb.
Use dtc command to recompile/update your dtb.

Thanks,
Shubhi

Yes, in JP4.3 changing the buffer size solves any communication problem.

Can you provide me with the command to recompile/update the dtb?
It’s the first time that I modify it

Hi,

sudo dtc -I dtb <nano-dtb> -o test.dts Open test.dts and modify it, then copy modified dts back to dtb sudo dtc -I dts test.dts -O dtb -o
In nano-dtb: use kernel dtb which is getting flashed
Let me know if you still face the issue.

Thanks

OK, so I must modify it on the host and then flash the dtb back using the flash.sh script…

Let me understand the patch, is the HW CS enabled in JP4.4?

actually it is fixed in J4.4. Previously, these properties were there but not inside controller-data, so driver was not actually using these. Now, driver updates these functionalities in the SPI HW controller. So, let’s try to remove and get back to J4.3 to check if this is the issue.
Also, you can update dtb in the target where dtbs are present in /boot/
Please check.

Thanks,
Shubhi

OK, I modified the DTB as you explained above, but no success.

This is what I did:

cd /boot/dtb
sudo dtc -I dtb tegra210-p3448-0000-p3449-0000-a02.dtb -o test.dts
sudo gedit test.dts

removed the controller-data nodes

sudo dtc -I dts test.dts -O dtb -o dtb tegra210-p3448-0000-p3449-0000-a02.dtb
sudo reboot

Have I missed something?

I noticed that I modified the wrong DTB file. The file /boot/extlinux/extlinux.conf points to another DTB:
/boot/tegra210-p3448-0000-p3449-0000-b00-user-custom.dtb.

I replicated the procedure above for this DTB file and tested again my application. NO SUCCESS. SPI still not working as expected.